RE: [SI-LIST] : A timing question in high speed bus

Bob Davis ([email protected])
Wed, 18 Nov 1998 21:36:54 -0800

Scott and Vinu

There is a slightly faster GTL+ part is available from Fairchild. However it
will not solve this problem with any margin. The spice deck for the TI part
is available and should be used with the appropriate parasitics added for
the pins and bond wires and power paths. The GTL+ that will work at 100Mhz
are the I/O cells built into the Intel and similar devices. The published
data on these parts - see Intel website - is much faster but does not allow
the type of interface that you are looking for.

To make a multidrop bus work for telecom application at 77.76 Mhz I had to
go back to good old PECL, as GTL would not cut it. This went from a -1ns
margin to +4ns margin including the propagation delay.

Good luck with your design.

Bob Davis, Consulting Engineer
Summit Computer Systems, Inc
Signal Integrity Specialists - High Speed, Critical PCB Design
408-353-2706
[email protected] , www.scsi.com

-----Original Message-----
From: [email protected]
[mailto:[email protected]] On Behalf Of Scott McMorrow
Sent: Wednesday, November 18, 1998 2:06 PM
To: [email protected]
Subject: RE: [SI-LIST] : A timing question in high speed bus

Vinu has correctly pointed out that for the SN74GTL16622 the timing
specifications are under a loading condition of 30 pF. This will,
of course, change the timing budget that I presented previously.
My simulations for this device indicate that there is a
400ps rising edge/450 ps falling edge (slow corner)
correction factor from the test load waveform to a driver
launching a wave into a 50 ohm transmission line terminated
at each end by 50 ohms. This must be subtracted from the timing
budget.

Thus, the system timing for these parts on a bus would be:

Tco 6.1 ns
Tsetup(data) 3.0 ns
Tjitter 0.25 ns
Tskew 0.4 ns
Tnoise 0.1 ns
Tthreshold 0.05 ns
Tcrosstalk 0.25 ns
driver load correction 0.45 ns

Total 9.70 ns

This leaves approximately 300 ps for signal flight time from
driver to receiver.

These parts are not appropriate for 100 MHz bus operation.

Regards,

Scott

--
___________________________
Scott McMorrow
Principal Engineer
SiQual

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