Simultaneous Switching

alaa alani (alaa@lsil.com)
Mon, 14 Jul 1997 12:02:58 +0100

Hi SI Colleagues,

The issue of simultaneous switching is very important in normal CMOS buffers due to the high dI/dt generated which may cause considerable ground bounce/power droop. In the case of differential buffers that use current steering design, the dI/dt is usually small and diminishes in a very short time yet when we switch a large number of differential buffers simultaneously we can notice some pulse width jitter in the transmitted signal. This is in the form of varying delay which can impact the setup and hold time particularly at high frequency (>250 MHz).

Now the question is do you think simultaneous switching is an issue in differential buffers which use current steering design? and if yes, has anyone done some analysis on the effect of SSO on pulse width jitter?

All feedback are welcome.

Regrads,

*****************************************************************************
Dr. Alaa F. Alani
Senior Signal Integrity Eng. Tel: +44 (0)1344-413383
LSI-Logic Europe Ltd. Fax: +44 (0)1344-413186
Greenwood House, London Road
Bracknell, Berks RG12 2UB E-Mail: alaa@lsil.com
England
*****************************************************************************