Re: Power/ground connections/bypassing on ICs

[email protected]
Mon, 28 Apr 97 10:26:50 -0700

Item Subject: Power/ground connections/bypassing on ICs


Two things to consider, first you want the ground reference to have the lowest
impedance path so that the noise margins are maintained and you also want the
Vcc path to have a capacitive source to supply transient currents.

So, in order to have a low impedance path to ground one would assume that the
best layout is to have the via to the ground plane be as close to the IC pin and
the via have the largest diameter hole possible to minimise the inductance of
the via. Don't forget to have the thermal reliefs eliminated if you don't have a
through hole lead (this is usually a battle between the manufacturing guys and
si/emi guys)

For the Vcc, you will want the capacitor pad as close to the IC lead as possible
and the ground side of the capacitor must be a low inductance path to ground.
Again, use the largest diameter hole to minimise inductance. There are layout
techniques that will let you do this and within a few mm of the capacitor pad
you can then place the via to the Vcc plane. Use a COG type capacitor for higher
frequency performance. Since the transient voltage equals R*i(t)+L*di/dt the
solution is obviously the reduction of the inductance.

The argument that the series L adds filtering is misleading. You are adding a
series impedance to the IC which allows it to loose noise margins since the
output voltages at the drivers will now be referenced to a voltage level
different than that of the ground plane.

My two pennies worth and I invite your comments/arguments!
Hans Mellberg

______________________________ Reply Separator _________________________________
Subject: Power/ground connections/bypassing on ICs
Author: Non-HP-ingraham ([email protected]) at hp-boise,shargw2
Date: 4/28/97 8:40 AM

I am tempted to open, once again, the discussion about how to connect
power and ground pins to ICs on a multi-layer PCB, and how best to
bypass them.

I have held the firm belief that IC power and ground pins should
always be tied right to their planes as soon as possible, with the
shortest trace lengths. Then bypass capacitors can be added near
those pins.

Some have suggested the alternative of bringing power and ground from
the planes, first to the bypass capacitor, and then to the IC pins,
something like this:

###| |###
| |
###| |###
vias | |
X=====###========###| |###
| | | |
X=====###========###| |###
bypass | |
capacitor ###| |###

I feel this is dangerous because of the added inductance. The
power/ground planes are your best high frequency bypass capacitor
(although a small one), so I'd think you want to get your IC pins
brought to them as quickly as possible, without wasting etch going to
a discrete capacitor which may not be very effective anyway if it's
above self resonance. Also the power and ground pin inductance is
effectively in series with all output drivers when they switch. So
I avoid this technique.

But I recently had a short discussion with an engineer who promoted
the latter, and insisted it was better in mixed-signal environments.
Most of my work has been straight digital lately, though I do find
myself surrounded by a smattering of mixed-signal components for such
things as ethernet.

The presumed justification is that these mixed-signal devices benefit
from the additional small filtering provided by the trace inductance.

By the way, the IC under discussion had all digital inputs and
outputs, but some internal clock re-timing, and no vendor
recommendations regarding power filtering.

Does it make sense to do this? Do I want to adopt a strategy of using
the first method for straight digital devices, and the second method
for mixed-signal devices that don't use filtered power?

Is it wise to do this with both power and ground leads? Or should
ground pins always route directly to the ground plane, with longer
traces in only the power leads? (Assuming no PECL, of course.)

Thanks for advice.
Andy Ingraham