______________________________ Reply Separator _________________________________
Subject: Re: decoupling/ bypass capacitors at connectors
Author: Non-HP-Larry.smith (Larry.smith@eng.sun.com) at hp-boise,shargw2
Date: 3/4/97 4:10 PM
> For 0.5ns requirements, the stitching has no effect except immediately
> adjacent to the signal trace or connectors. The displacement current will
> find the most proximal structure to propagate the image current.
>
> Hans Mellberg
> Consultant
>
The stitching of ground planes every square inch of the board will have
significant effect. Imagine a signal on the top layer of the card
that is referenced to a ground plane immediately below. The signal
goes down a via, through the board and takes off on a trace referenced
to another ground plane on the bottom of the board.
The question is, what happens to the return current. If the rise time
is .5 nSec, the 'length' of the rise time will be 3 inches, assuming 6
inches/nSec. (If these are exterior traces, the velocity may be closer
to 9 inches/nSec, making the distance traveled in the rise time 4.5
inches.)
Suppose there is a ground plane stitch via within 1 inch of the signal
via (1/3 of a rise time distance). True, there will be an impedance
discontinuity as signal current must depart from the return current as
the currents go through the vias. But, the time of flight (1/6 nSec)
will allow for 3 reflections across the impedance discontinuity during
the rise time. If we can get 3 reflections during the rise time, the
impedance discontinuity has minimal effect on the waveform.
If one of the reference planes is power, then decoupling will be
involved in the current path. The fidelity of the edge will be
degraded if a 'short' path is not provided for the return current.
Ground and power plane bounce will occur at via locations if this
path is not provided.
Larry Smith
Sun Microsystems