Re: [SI-LIST] : How to identify SSO

Art Collard (
Thu, 8 Jan 1998 08:47:54 -0600

> One thing that has always concerned me with SSO is the affect of the =
> drop on non-switching signals. Theses signal would have noise on them
> that would mimic the VCC noise on chip (since their outputs are
> effectively shorted to VCC).

Andrew Ingraham wrote:

> Indeed. Even worse, since noise margin is usually smaller in the
> low state than the high state, is the GND bounce killing your noise
> margin on those outputs that are supposed to be LOW.

> You may need to assume that ALL outputs go indeterminate on every
> clock cycle, whether they switch or not. Clock or clock-like
> outputs need special treatment to keep them usable as clocks.

These are the observations I can conclude about ground bounce from an IC =
point of view:

1) It can occur on both the Vss and Vdd rails.=20
2) Bounce is directly related to a large instantaneous current flow =
through a =20
power supply inductance.=20
4) Bounce is not due to the output capacitance or inductance.=20
5) Ringing is a function of the output loading.=20
6) Bounce is dependent on the physical location of a driver as well as =
the =20
number of outputs which switch at the same time with respect to a =
pwr/gnd =20
7) Bounce is directly related to the di/dt of the output driver gate =
(switching =20
speed of the pre-driver).=20
8) Ground bounce can occur when an output is switching and the =
complementary =20
output gate has turned off while its supply was ringing.
9) Powering sections of a chip separately from the pad drivers (pin =
drivers) and=20
grouping smaller amounts of pad drivers per pwr/gnd pin helps.

What I have seen is AC timing failures due to current starving and or =
noise on=20
the IC power/ground rails. Plotting the pins which fail reveals either =
or bumps on the signal at the time of AC timing measurement. The fail is =
to reading a voltage level below Voh or above Vol.=20

The other point here is that the pwr/gnd become a source for EMI.