si-list.mail: [SI-LIST] : A timing question in high speed bus

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Dear list,
I have to design a backplane bus with about 100M Hz clock and the =
transmission distance wanted as long as it can, using GTL . The design =
is to be a Synchronous clock one . The component we want to use as =
transceiver is SN74GTL16622, the specification said that it can function =
up to 200 Mhz clock frequency .
But I have a puzzle about the high speed bus's timing:=20
You know, the formula: "TFLT_MAX <=3DClock Period - TCO_MAX - TSU_MIN =
-CLKSKEW- CLKJITTER"(TFLT_MAX is the largest flight time a network will =
experience under all variation of conditions,TCO_MAX is the maximum =
colok to output specification, TSU_MIN is the minimum required time =
specified to setup before the clock,CLKJITTER is the maximum clock edge =
to edge variation,CLKSKEW is the maximum variation between components =
receiving the same clock edge.) For 100MHz bus,the Clock Period is 10ns, =
and for TI's SN74GTL16622,TCO_MAX is 6.1ns (maximum of TPLH from CLKAB =
to B is 6.1ns),TSU_MIN is 2.6ns. In some papers such as Intel's Pentium =
II Processor GTL+ Guidelines, they give the CLKSKEW and CLKJITTER is =
about 0.4ns and 0.25ns. Then the TFLT_MAX is about only 0.65ns.=20
It's clear that the flight time is not enough , for example, in the =
NESA's paper "An Innovative Distributed Termination Scheme for GTL =
Backplane Bus Designs", they used the GTL+ to implement 100MHz bus , the =
delay of 9 inches distance is 1.62ns (this delay time is not the =
flight time, it's just a part of it.), and my design have to be much =
longer than 9 inches . So I am puzzled , is the calculation wrong, or =
others?
How can I settle the timing question ?
(By the way, the maximum of TPLH from CLKAB to B is 6.1ns , how can it =
work on 200MHz clock frequency ?)

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I have to design a backplane bus with about 100M Hz clock and = the=20 transmission distance wanted as long as it can, using GTL . The design = is to be=20 a Synchronous clock one . The component we want to use as transceiver is = SN74GTL16622, the specification said that it can function up to 200 Mhz = clock=20 frequency .

But I have a puzzle about = the high=20 speed bus's timing:
You know, the formula: "TFLT_MAX <=3DClock Period - TCO_MAX - TSU_MIN -CLKSKEW- CLKJITTER"(TFLT_MAX is the = largest flight=20 time a network will experience under all variation of conditions,TCO_MAX is the maximum colok to output specification, = TSU_MIN is the minimum required time specified to setup = before the=20 clock,CLKJITTER is the maximum clock edge to edge=20 variation,CLKSKEW is the maximum variation between = components receiving the same clock edge.) For 100MHz bus,the Clock = Period is=20 10ns, and for TI's SN74GTL16622,TCO_MAX is 6.1ns = (maximum of=20 TPLH from CLKAB to B is 6.1ns),TSU_MIN=20 is 2.6ns. In some papers such as Intel's Pentium II Processor GTL+ = Guidelines,=20 they give the CLKSKEW and CLKJITTER is=20 about 0.4ns and 0.25ns. Then the TFLT_MAX is about = only=20 0.65ns.
It's clear=20 that the flight time is not enough , for example, in the NESA's paper = "An=20 Innovative Distributed Termination Scheme for GTL Backplane Bus = Designs",=20 they used the GTL+ to implement 100MHz bus , the delay of 9 inches = distance is 1.62ns (this delay time is not the flight time, it's = just a=20 part of it.), and my design have to be much longer than 9 inches . = So I am=20 puzzled , is the calculation wrong, or = others?
How=20 can I settle the timing question ?