[SI-LIST] : Horror stories ?

Roger Gravrok (rjg@sequent.com)
Thu, 11 Sep 1997 10:24:56 -0700

The school of hard knocks teaches some pretty tough lessons.
We could all profit by not repeating our own (or other's) mistakes.
I would like to start a discussion about CMOS-design horror stories.

What are some items that you did, (or wish you had) checked
before releasing a CMOS design that could have (or did)
create a horror story in first silicon? I would like to focus on
high-performance digital, but basic stupidity is not selective.

Some thoughts to get you started.....

Die orientation (when flipped over in the package, it didn't match up).

Power distribution mistakes; weak to core, shorts, ring cuts, SSO...

PLL problems, substrate coupling....

Clock distribution & skew....

Sufficient via counts in all current paths within an I/O cell...

Latchup....

With Halloween just around the corner, what are your horror stories?

-Roger