Some additional questions:
1. Does anyone on the LIST have PCB design rules for this geometry
(serpentine) that they have validated on the bench? (e.g. not just a
rule of thumb)
2. Or, have a decent model to comprehend the effects of this geometry
(cross-coupling due to parallelism, any additional degradation of rising
edge, etc?)
Unimportant question: At what frequencies/geometry dimensions might we
have to worry about signal phase relations due to signals rounding a
corner in this zig-zag (serpenting arrangement)? (e.g. skin effect
essentially pushes the signal to the outer edges of the trace, around a
corner, the inside radius is a shorter path than the outside radius.
When the trace "straightens" won't there be a phase dispersion across
the trace width?)
Thanks for any help.
Brett
> I would like to echo that this zip-zag trace pattern has been known
> and oberserved in the lab to reduce the total expected delay. I
> came across a situation when I was using PCB trace to add some "skew"
> into the clock nets. The actual clock skew that was induced thru this
> kind of topology was measured to be less than the min. expected delay
> by 5% to 10%.
>
> I ended up running the serpentine in a wider gap (24 mil to 30 mil)
> to allow an accurate clock skew distribution. But, this costed us
> more space on the PCB to delay the clocks.
>
> Michael Chin
> Cisco Systems, Inc
-- ------------------------------------------------------------------------ Brett Grossman __ ___ Intel Tooling Operations __ /\ \__ /\_ \ Phone: 408-765-2619 /\_\ ___\ \ ,_\ \//\ \ Fax: 408-765-2518 \/\ \ /' _ `\ \ \/ __ \ \ \ email: [email protected] \ \ \/\ \/\ \ \ \_ /'__`\\_\ \_ \ \_\ \_\ \_\ \__/\ __//\____\ \/_/\/_/\/_/\/__\ \____\/____/ The views expressed are my own. \/____/ ------------------------------------------------------------------------