Design Engineers wanted in Pacific NW!

the shadow ([email protected])
Wed, 5 Feb 1997 07:39:22 -0800

Please post the following jobs for High Speed Design Engineers
for a Fortune 500 company in the pacific northwest.

Sr. Hardware Engineer
Fortune 500 Semiconductor Company
in Pacific Northwest

The successful Sr. Hardware Engineer for this Fortune 500 Semiconductor
company will conduct or participate in multidisciplinary research in
the design, development, testing and utilization of information
processing hardware and/or electrical components, mechanisms,
materials, and/or circuitry, processes, packaging, and cabinetry for
central processing units (CPUs) and/or peripheral equipment. Prepare
specifications, evaluate vendors, and analyze test reports. Ensure
products conform to standards and specifications. Develop plans and
cost estimates and assesses projects to analyze risk. Develop
procedures, analysis and design for computer components, products, and
systems. Initiate, guide, and coordinate overall design and development
of new ideas and products. BS or MS degree required plus a minimum of 4
years experience. Please email a resume in ASCII format to:
[email protected]

Staff Hardware Engineer
Fortune 500 Semiconductor Company
in Pacific Northwest

Candidate will be a member of the team responsible for design and
validation of current and future generation products. Candidate will
lead a team with representatives from many internal design groups
responsible for defining and ensuring the successful development and
implementation of front side or back side bus. The candidate will also
be responsible for the overall timing budget for the various components
in addition to providing technical contributions in the areas of
packaging, I/O buffer design, and system interconnect design
(including specification of topology and system design requirements).
Specific duties will include developing the timing budget and design
targets for the various groups, developing package and system network
models, performing extensive simulations and analysis using both Quad
and HSpice simulation environments, driving layout studies to validate
simulations, and documenting the results through presentations and

Candidate must have solid technical background in design of high speed
systems including clock and power distribution, transmission line
analysis, and noise containment. A proven tack record of successful
completion of H/W design projects and experience with analog circuit
simulation is essential. Must also be able to demonstrate the ability
to prioritize and handle multiple tasks, strong initiative and
self-notification coupled with the ability to work under minimal
supervision. MSEE or BSEE required along with at least 5 years relevant
experience. Please email a resume in ASCII format to:
r[email protected]