Here's a dumb question for you: Are you sure that the
RFI you're trying to supress is directly associated with a signal
which is being carried on one of the ASIC signal pins? The reason
I ask is that I have heard of more than a few cases where RFI from
a chip was coming from a process that was internal to the chip but
which was not a component of a signal.
If this interference is showing up on your signal pins and
is not a Fourier term from the signal on that (those) pin(s) then
you might try a notch filter, providing n is sufficiently high so
that the filter doesn't degrade the intended signal.
If the interference is being radiated then you may have to try
to shield the ASIC itself in some way.
On Dec 3, 6:15pm, Manix Velu wrote:
> Subject: [SI-LIST] : EMC Issues with ASIC design
> Can anyone help in identifying RFI emissions from our ASIC that runs
> at 12MHz?
> Our OEMs report that the emissions are from our ASIC only. The RFI is
> coming at the n'th harmonics of the 12MHz. We are struggling to
> suppress this by adding capacitors on the 12mA switching I/O pads of
> the ASIC, reducing the loop-area covered by the external 12MHz
> crystal circuitry, added a 47 ohms series resistor on the XTOUT pin
> of the ASIC to the crystal, grounded the shields of the interface
> connectors...and yet...there is no improvment.
> Could any of you please throw some light on this issue? Is there any
> thumb rules that we can follow to supress RFI for such end products?
> Besides this, could any of you please advise, what are the EMC
> fundamentals that we should consider while we deisgn the CMOS ASICs
> that has the gate count of less than 12K and runs at 12 to 24MHz?
> Thanks in Advance,
> Manix Velu.
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>-- End of excerpt from Manix Velu