Re: [SI-LIST] : IC DIE SHRINK

Purge (sams@pacifier.com)
Sun, 19 Jul 1998 00:48:49 -0700

Don't forget about the internal timing changing as well. I had a
problem a few years back with some FPGA's from Xilinx. They (Xilinx)
did a die shrink but didn't tell us so we happily continued to use the
old code image w/ the new die shrunk FPGA's. During some thermal
testing, we were continuously getting sporadic failures. After it was
all said and done, it turned out that the new FPGA's were at fault. A
quick recompile with the new compiler that supported the newer chips and
everything was fine.

SamS

Poulet P. wrote:
>
> Si list,
>
> My company once had a design working for several years until they shrank
> the die of a CPLD. Since then we had been experiencing sporadic failures
> and crashes until we found a solution. ( Terminating a few critical
> input signals ). So far not much new.
> My question is does any body know what could be the effects of a die
> shrink ( besides time delay and rise/fall time) on a component like a
> CPLD 2000 gates. I compared timing delays and rise time between the two
> processes and there were ( as claimed by the manufacturer ) almost the
> same.
> I could never get any clear answer from the manufacturer.
>
> Thanks
>
> --
> Philippe Poulet
> RICOH Corp