Re: [SI-LIST] : Decoupling:routing

Tom Zimmerman (tzimmer@fnal.gov)
Thu, 30 Apr 1998 09:14:07 -0500 (CDT)

Hi all,

I had several responses to my post the other day about decoupling for mixed
signal systems.

I'd like to elaborate a little (actually a lot) on what I posted, and
maybe clear up a few misconceptions.

I'll start by saying that what we're doing is for a rather esoteric application
and may have a unique set of problems because of that. We are designing a
full custom multichannel detector readout chip for a high energy physics
detector at Fermilab. A large detector system will have lots of these chips
connected directly to silicon strip detectors. We have to figure out the best
way to design these chips, mount them, and supply power to them. The hardest
part is that the chip
is mixed signal: it has a very sensitive charge integrator on the front end,
which must resolve detector signals that are a fraction of a fC (femtocoulomb),
on the order of 1000 electrons! Then the back end of the same chip is
digitizing and reading out the acquired levels at high rate, so there is lots
of digital noise occurring at the same time that low level signals are being
acquired on the front end.

So, this is not a "typical" system with a PC board that has pwr/gnd planes
and a bunch of commercial digital and maybe analog chips. The subsystem
we are designing is ONE full custom mixed signal chip on a tiny board, which
connects to one detector. How to reference everything and connect
the analog and digital power and ground, etc. for this chip and detector
are important questions for us. This may be a different situation
than what most of you encounter, but I think we have learned some important
things which may be of help to others.

To try to summarize without too much detail, we learned that two of the
important issues for our mixed signal design are: 1)substrate coupling on a
mixed signal chip (digital pollutes analog), 2)clean ground referencing for
the system. The requirements for clean reference are rather extreme in our
system since the front end is so sensitive. A fraction of a mv across two
different points on the "ground" can really mess up the analog section. This
is how we arrived at the "digital pwr/gnd pins to cap, then cap to ground
plane" digital bypass method. There are no power planes, since there is only
one big full custom chip on this small board, with two separate supplies,
digital and analog. There must be one ground reference plane to reference
everything to, including the digital ground (DGND). Many people insisted that
there should be two separate ground planes, digital and analog, so that the
digital doesn't pollute the analog. However, this would be a disaster on a
mixed signal chip like this, since the DGND could then be bouncing wildly
with respect to analog stuff and couple to it. The trick is to reference
DGND to the "analog reference plane", but keep it from polluting that reference.
Initially we just connected DGND to the plane, then some finite distance away
bypassed the DVDD wire to the plane. What we saw was that 100mA-ish digital
current transients of course flowed through the plane and caused mV-ish
voltage differences between different points on the plane. We inferred this
by looking at the output of the analog front end charge integrator, which
operates at MHz-ish bandwidth. Since its
analog VDD (AVDD) is bypassed to the plane, digital noise on the plane is
fed right into AVDD and affects the integrator output. That's when we changed
our method to run the DGND pin NOT directly to the plane, but to the cap, then
from the cap to the plane. The DVDD supply wire just feeds the other side of
the cap, which then goes to the DVDD chip pin. This cleaned things up nicely,
since the large currents are kept in the local loop of chip-cap, and off of the
plane. The integrator output was much less affected by the digital activity.
This all seems very obvious now, but it took us a while to figure
this out. I'm just used to connecting everything to the ground plane as
soon as possible!

I think that the tradeoff here is that you introduce a bit longer effective
lead length or inductance in the digital supply to obtain the benefit of
cleaner ground. I don't have much experience with other types of systems,
but I suspect that on systems where the ground referencing isn't quite so
critical, you might want to minimize the lead length and therefore the supply
bounce, at the expense of currents running through the ground plane. (???)
That is, if you can tolerate some level of voltage differences across the
plane. Where 1 mV would be a disaster for us, it could be insignificant for
others. I'd be very interested in hearing any comments on this from
designers of other systems. How much do people worry about this kind of
thing?

I also wanted to comment on the other important issue for us: substrate
coupling. We found out that for an IC built on an epi process (low
resistivity substrate), the inductance between the substrate (back plane) and
the system ground is a critical parameter. Great article about this in
IEEE JSS, March 96 by Gharpurey and Meyer. This inductance is a common
impedance between digital and analog sections on the same chip. Lucky for
us, our application is very atypical and in fact requires that our chip NOT
be packaged, but mounted as a bare die directly to the board (space and
mass constraints inside the detector). This couldn't be better for minimizing
substrate coupling. We lap and backplate the wafers so that the chips can
be glued (conductively) directly to the ground plane/die pad on the board.
Then the substrate to system ground inductance is VERY low. This works
really well and virtually eliminates substrate coupling! In fact, we also
use the substrate to conduct all the analog ground current. There are no
AGND pads on the chip; all analog circuits are referenced through the
backplane RIGHT to the system ground. The chip substrate is effectively
just an extension of the system ground plane. DGND is NOT referenced through
the substrate, but brought out to a pad, of course, for the reasons discussed
before. Has anybody else had this experience or used this technique?

A colleague of mine is building a fairly large PC board for another project
and we have been discussing these issues. His board has a big all-digital
section, and then a smaller analog section. The analog chips each have one
digital output (a comparator output) which runs over to the digital section.
He has board layers which are devoted exclusively to power and to ground.
He's trying to bypass all the digital chips with the chip-cap-plane method,
but it's a lot of work to do it that way, and he's not sure it's worth it.
His situation is different than mine, and I'm not sure how to advise
him. Have other people done this, and what are your experiences? His
other question is whether to separate the ground planes for the digital and
analog sections or not, and if so, do you reference them together at just
one point? I tend to think there should be one common plane, but that's
because of the experience I had, which may be quite different on a large
mixed signal board with lots of parts.??

Hope I've not been too long-winded, but I thought others might benefit from
my experience, even though it may be an atypical situation. Comments
welcome!

Tom Zimmerman
Fermilab
tzimmer@fnal.gov