RE: [SI-LIST] : Excessive clock overshoot

Charles Hill (chuckh@csn.net)
Wed, 13 May 1998 22:06:17 -0600

Fabrizio,

I have seen this many times before with FCT logic. In my experience it is
the worst choice of logic families from a signal integrity point of view.
The edge speed is very fast, and current drive is very high, and so the
speed is fast---but that is bad for signal integrity. I suggest you try
ABT, or F. There is also other types of FCT which are intended to be more
"SI friendly".

Charles Hill, consultant
chuckh@altaeng.com

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From: fabrizio
zanella[SMTP:fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com]
Reply To: fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com
Sent: Wednesday, May 13, 1998 2:16 PM
To: si-list@silab.Eng.Sun.COM
Subject: [SI-LIST] : Excessive clock overshoot

I have a question regarding an FCT clock (TTL levels) driving a heavily
loaded backplane. On the driver pin we see excessive overshoot on the L-H
transition which increases as we increase the clock frequency. This
overshoot goes from 5V at 33MHz to 6.5-7.0V at 45MHz. The stub impedance
is 75 ohms, backplane impedance 25 ohms loaded. There is a clamping diode
on the H-L side but not on the L-H. The H-L side does not have any
undershoot.
I have asked the manufacturer and they have never seen this phenomena, nor
do they have an explanation for it.
Any ideas on what could be causing this?

thanks and regards,
Fabrizio Zanella
Design Engineer
EMC Corporation
508-435-1000
fzanella@emc.com