As a first-order approximation, you can estimate the impedance of each
signal layer using your formulas by assuming no conductor(s) on the
neighboring signal layer(s). Or, use an EM modeling tool.
We have used similar to the S-S-G-P-S-S arrangement (but more than six
total layers), where the two outermost layers on each side were signal.
The surface layers were for dispersion etch only. It apparently makes
some difference in the routability of the board. Trace lengths on
these surface layers must be minimized, because of the impedance
mismatch and the greater crosstalk to the adjacent (embedded
microstrip) layer. If the trace length on the outer layer is much
shorter than a wavelength at your highest harmonic, then it can work.