Although the numerous comments are correct, in my opinion they may be too
confusing for a person who simply asks what the differential impedance is.
Here is a little different view of the same topic.
Imagine a differential pair (hence carrying signals of opposite polarity)
above ground plane. Assume that the pair has longitudinal symmetry, so we
only need to look in two dimensional cross-section.
The E-field lines will be concentrated from the traces to the planes and
between the traces. I can't depict it well here, but they will go from
"+"-trace to "-"-trace, from "+" to plane and from plane to "-" trace. Due
to symmetry, we can add another ground half-plane perpendicular to the
first plane and in half-way between the traces. That would not change the
field configuration. Now, we can simply remove one half of the picture.
The field distribution in the corner embraced by the planes will not change.
The characteristic impedance of that trace is the odd-mode impedance Zodd,
and is one half of the differential mode impedance (which is
Hence, Zdiff= 2xZodd.
If the horizontal distance between the trace and the vertical imaginary
plane increases, and gets larger than the height above the plane, the Zodd
approaches Zo of a single trace above the ground plane (coupling of the
trace to the vertical plane goes to zero). 3xtrace width (3w) is a good
rule to determine the boundary, if the height of trace is close to its width.
If you assume 5 mil as the minimum trace width or separation, and er=4.5,
than you will not be able to make 100-Ohm or higher-impedance differential
pair in the internal layers of a PCB. The er is simply to high, and the
differential impedance will be lower than 100 Ohm. This is valid for usual
dielectric thicknesses and trace widths on the PC boards. In any case, you
need some software (I mostly use LINPAR from Artech House) to calculate the
In order to get 100 Ohm, the differential pairs must be on the outer
layers. I usually design 100 Ohm pairs on the outer layer, with 6 mil trace
width, 6 mil separation and 5 mil dielectric height above ground plane.
When you design for impedance, be also aware that the manufacturing
tolerance can easily be 20%.
The SI-people will probably be happy as long as the trace impedance is in
the wanted range. That can be achieved by keeping the cross-section ratio
of the trace geometry constant. Even if the traces are not very close to
each other, the correct impedance can be designed, and it will be OK from
the SI point of view as long as there is enough clearance from each trace
to any other trace/component on the PCB.
However, the EMI produced by a differential pair in which the traces are
not very closely coupled to each other will significantly increase. EMI
will also increase with increase of the height of traces above the ground
plane. Therefore, when you design keep the distance between the
differential traces as small as possible, use the minimum dielectric height
from the ground plane (what I do by using 6mil/6mil/5mil pairs), and have
some clearance (here comes 3w handy again) from the pairs to anything else
on the board. You can evaluate the effect on EMI by doing either experiment
or try to use some EM-software, e.g. NEC. With a constant total
trace-length, two times larger separation means 6 dB more contribution to
total EMI from a board. Keeping the traces close and low also helps to
increase immunity of the differential pairs.
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