Good comments. As my colleague Larry Smith alluded to in an earlier message, a
significant and measureable part of the mounted inductance is the spreading inductance
of the power planes to which the capacitors are connected.
Our group has obtained very good model to measurement correlation between
Hspice simulations and lab measurements where we were able to predict the
change in capacitor resonance caused by changing the location where the
capacitor was mounted on a board. It can be shown that the spreading inductance
is highest at board corners and lowest at the board center with intermediate
values seen at board edges. Compared to the board center, the inductance seen
at an edge location is about 2X and about 4X at a corner location.
If you are placing bypass capacitors on your layout hoping a particular
resonant frequency will provide a low impedance at a particular frequency,
you can be a ways off if the spreading inductance effect is ignored. Note that
this is most true at high frequencies. While the spreading inductance may
change by a factor of 4, remember that depending on the plane separation
this may equate to a change of from 100pH to 400pH for relatively widely
spaced planes (~15mils) to a delta of perhaps 15pH to 60pH for closely
spaced planes. Also bear in mind that these inductances comprise only
about 10% of the total mounted loop inductance in most cases, so the
change is the capacitors resonant frequency may not be great, but it is
measureable and may be siginificant in some applications.
The paper by Larry and Tanmoy from Sun and John Prymak from Kemet to be
presented at EPEP in October will have more details on this as well
as other significant findings related to the accurate characterization
of chip capacitors.