Re: [SI-LIST] : Down-bond in chip packaging

Yehuda D. Yizraeli (yehuda@zoran.co.il)
Wed, 11 Feb 1998 23:15:45 +0200 (EET)

Hi again,

The core logic is not sensitive to this asymetry, however the
input buffer logic does and it is put on the core logic. Putting the core
VSS and the periphery on the same plate might cause the VSS_Core to ring
compared to the board VSS to which the input levels are referenced by the
driver signal. Backplane/substrate is not the best conductor for
current flow (although i heard of silicon suppliers doing it, but for
noise injection its good enough.

Thanks for the response, yehuda

>
> Yehuda D. Yizraeli wrote:
>
> > I will agree with your approach if the package has rails, namely
> > separated power planes for its use, however, i meant a plane-less package
> > inwhich the cavity is used as the down-bond plane which means noise is injected
> > to the whole core, doesn't it..?
>
> Ah! Something like a PQFP, then.
>
> Be careful here. The die attach isn't really a reliable
> electrical connection to the bulk silicon, and if your
> package is typical it doesn't have especially better feeds
> than the signal connections. Since there are bulk connections
> all through the core, you may as well tie the core VSS to
> the plate. This is also true since the core is less sensitive
> to supply symmetry than the I/O ring is.
>
> The PLL supplies, though, should still be isolated.
>
> > > > I am inveswtigating the various options of using the down bonds
> > > > for our design. naturaly, one would like to connect all the VSS to the
> > > > down-bond plate. However, the periphery supply, which makes the most
> > > > noise, can then inject noise into the core logic, especialy to the PLL
> > > > circuitry through the substrate (influencing input buffers' trip-point
> > > > as well). So, my conclusion is to conect core and other non periphery
> > > > VSS to the down-bond plate (paddle) and the periphery should be directly
> > > > connected to the packages' pins.
> > > >
> > > > Do u agree with the analysis, can u point me to some areticles
> > > > and/or literture on the subject..?
> > >
> > > Our standard practice is just the opposite. Core current is
> > > generally balanced so onchip bypassing takes care of the worst
> > > of the high-frequency components, while most I/O types are
> > > unbalanced and heavily dependent on supply inductance. We
> > > run the I/O ring VSS and VDD supplies to the package rails
> > > and supply core through either signal or secondary supply
> > > balls. Either way, PLL supplies are as completely isolated
> > > as possible, with no connection to either core or I/O supplies
> > > short of the PWB planes.
>
> --
> D. C. Sessions
> dc.sessions@tempe.vlsi.com
>

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   Yehuda D. Yizraeli

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