Preparation for system level simulation with XTK is as follows:
Individual designs are translated from various host CAD systems
into a standard uniform format. From this intermediate format,
designs are concatenated during the translation into one cohesive
The translation is guided by user defined rules of signal trace
proximity and parallelism in determining transmission line cross-
section geometries. The proximity and parallelism rules apply across
the modules. E.g. Parallelism is considered everywhere between nets
which couple across modules.
Multiple instances of one module can be used in a system definition.
E.g. for simulation of SIMMS on a memory interface or generic
plug-in adaptor cards on a backplane.
The overhead associated with system level simulation is two user
created ASCII files. The first describes a design hierarchy and
the second specifies board-to-board connections. Support is
incorporated to model connector parasitics.
Quad Design Technology (A Viewlogic Company)
# Design GCF/TOP Hierarchical Level Instance ID
# ============= ================== ===========
mem_board/mem_board.gcf 3 a
mem_board/mem_board.gcf 3 b
mem_board/mem_board.gcf 3 c
mem_board/mem_board.gcf 3 d
mother:J1 = board1:P1
mother:J2 = board2:P1
board1:J5 = cable:P1
board1:U1 = mem_board_a:P1
board1:U2 = mem_board_b:P1
cable:P2 = board2:J5
board2:U1 = mem_board_c:P1
board2:U2 = mem_board_d:P1
> Can anyone post information concerning how Viewlogic's XTK
> calculates crosstalk across modules. Does it read the module
> databases and create one network which is 'simulated' ,
> or is there another algorithm it uses ? Any experience
> with its accuracy, ease of use and flexability ?
> regards, and thanks in advance,
> Bob Haller
> -----------------Forwarded item dated 25-JUL-1996 12:19:57.36-----------------
> From: US1RMC::"Raymond.Anderson@Eng.Sun.COM" "Ray Anderson"
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