Without the presence of the floating plane, I would think one could
obtain a good package model by simply considering the ground,
signal, and power paths as filaments and use the Grover
inductance formulas or an appropriate EM tool to compute
the mutual and self inductances.
Now with a floating metal plane added for a stiffener for the BGA
laminate, one might be tempted to place the plane in close
proximity to the signal leads to provide a controlled impedance
environment. Since the floating plane cannot provide continuous
current, I would suspect it would do little to reduce the inductive
coupling, especially for the case when all outputs switch in phase.
However, the floating plane should cause the signals to be capacitively
coupled more strongly together to one another and to the power
and ground signals. If so, then what is the resultant noise behavior
when compared with a classic "inductive-only" coupling response?
How does the driver output impedances affect the response?
Assuming I have a good package and wire bond models and good
transistor level (not IBIS) driver models, what else would be required
for a reasonably accurate SSN simulation? For example, how important
is it to add the CMOS logic core well capacitances? Is there anything
obvious that I missed?
Any thoughts about how the floating plane would affect the EMI
emissions?
I would greatly appreciate any suggestions.
Mike
-- _______________________________________________________________ Mike Degerstrom Email: [email protected] Mayo Clinic - Gugg. Bldg. RM 1011-B Phone: (507) 284-3292 Rochester, MN 55905 FAX: (507) 284-9171 WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html _______________________________________________________________