Re: [SI-LIST] : IC DIE SHRINK

Scott McMorrow (scottmc@teleport.com)
Fri, 10 Jul 1998 15:40:46 -0700

The answer is that stuff gets faster if left uncontrolled.
It appears that the output drivers were well controlled
during the process shrink. Although to be sure the measurements
need to be made with a scope that has sufficiently high
bandwidth (> 1GHz). However, inputs become faster,switch
faster and become more susceptable to signal integrity
issues that were ignored (filtered out) before. Technically,
the gain bandwidth product of the inputs becomes higher
during the process shrink. CPLDs are extremely sensitive
to this effect, since the array itself often acts as a filter.

Scott

Poulet P. wrote:

> Si list,
>
> My company once had a design working for several years until they shrank
> the die of a CPLD. Since then we had been experiencing sporadic failures
> and crashes until we found a solution. ( Terminating a few critical
> input signals ). So far not much new.
> My question is does any body know what could be the effects of a die
> shrink ( besides time delay and rise/fall time) on a component like a
> CPLD 2000 gates. I compared timing delays and rise time between the two
> processes and there were ( as claimed by the manufacturer ) almost the
> same.
> I could never get any clear answer from the manufacturer.
>
> Thanks
>
> --
> Philippe Poulet
> RICOH Corp

--
___________________________
Scott McMorrow
Principal Engineer
SiQual

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