The issue of Static Signal Electromigration analysis
has been addressed by Nagaraj NS et al. in a paper
(pg. 572-577) in DAC Proceedings 1998. The issue has been
addressed from practical perspective (TMS320C6201). This
is one of the relevant issue for large cell based design.
(His e-mail address: email@example.com).
There are two more papers in the same proceedings:
A. Figures of Merit to Characterise the Importance
of On-Chip Inductance by Yehea I Ismail et al.
B. Layout Techniques for Minimizing On_Chip
Interconnect Self Inductance by Yehia Massoud et al.
See if you find these relevant.
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