Re: SI- Termination Comments Wa

Arpad Muranyi (Arpad_Muranyi@ccm.fm.intel.com)
Mon, 22 Apr 96 16:28:07 PST

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Norman,

Your questions are addressing issues that is the bread and butter of every
signal integrity engineer. There are lot of books out there which address these
issues, including my good old favorite, the Motorola ECL Design Handbook.

Everything you say in your EMAIL makes sense.

The impedance will vary with distance to GND plane, but ~50~75 Ohms are in the
range of numbers I have seen.

If possible avoid changing layers.

Chain topology is better than having stubs.

Parallel terminations do draw DC current which normal buffers are not designed
to do, so your Vol and Voh might be "loaded" depending on which supply you are
using for your termination.

5 ns rise/fall times are more forgiving than 1 ns, but to decide what you can do
you need to know the length of the trace also. This goes for the length of the
stubs as well. With slower rise/fall times you can generally have longer stubs.
The best, however, is not having stubs at all...

There are no short, clear answers to these questions. Most often you need to
run a lot of simulations and learn from the simulation results... Most of the
questions you are asking can be answered by parameterized Monte Carlo type
simulations and plotting the results in a statistical manner. This is how most
of us figure out the best solutions and the design space for a given design,
topology, loading condition, etc...

Good luck,

Arpad Muranyi
Intel Corporation
================================================================================
Subject: Time:3:44 =
PM
OFFICE MEMO SI- Termination Comments Wanted =
Date:4/19/96

I am currently working on a mid-speed (<50MHz) digital circuit pack and =
would like to proper terminate some long lines(up to 15 inches). It =
consists of CPU, DSP, SRAM, Flash etc. I am approaching the problem by =
using Daisy-Chained tracks and AC terminations. There are some findings =
that I would like your comments:

1. When using uncontrolled-impedance FR4 PCB, based on my calculation on =
a 6 layer board, the micro-strip (8 mil) Z0 is about 75 Ohm and the =
micro-strip Z0 is about 45 Ohm. That means a mismatch every time I =
switch layers. Does anyone has experience on this? Does it matter for 5 =
ns rise time? How about 1ns rise time?

2. My EDA simulation package showed that after termination, my signals =
do not look much cleaner. In fact, it look worse and seems to be loaded =
down (Vpeak is about 3.5-4V instead of 5V). Does this make sense?

3. At want point could I use T instead of Daisy-Chain so that the stub =
look like capacitance, no transmission lines? A lot of time daisy chain =
line is longer than a treed line.

All comments on this matter are welcome.

Thank you.

Norman Wong
Hardware Design Engineer
Nortel, Wireless Development Center, Calgary

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To: Signal Intergity Group <si-list@silab.Eng.Sun.COM>
Subject: SI- Termination Comments Wa
From: Norman Wong <Norman.Wong.0139127@nt.com>
Date: 19 Apr 1996 16:55:25 -0400
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