Re: [SI-LIST] : another stack-up question

Vinu Arumugham (vinu@cisco.com)
Fri, 01 May 1998 17:05:44 -0700

D. C. Sessions wrote:

> TINSTAG -- There Is No Such Thing As Ground. Kirchoff's
> Law is what's happening here. On a rising edge, the driver
> creates a path between the Vdd node and a signal line. As the
> line charges, some current is induced on both the Vdd and adjacent
> planes, and eventually (via the receiver) in the Vdd and Vss
> connections of the receiving device. Ultimately these currents
> must get back to the driver's Vdd node.
>
> About the best we can do is have about half of them on the Vdd
> plane and half on Vss, but that at least gives symmetrical loop
> impedances. If there are two Vss planes and no Vdd plane, the
> rising edges will have higher loop impedances than the falling
> edges and the signals will reflect this.

The rising and falling edges will see the same impedance.
The signal trace and the Vss plane form a transmission line. For the rising edge,
the circuit consists of the bypass capacitor, the pull-up structure and the
transmission line. For the falling edge, the circuit consists of the pull-down
structure and the same transmission line. How does an impedance asymmetry between
the edges arise?

> Also note that even in less-demanding systems where there isn't
> a problem with the signals themselves, doubling the amount of
> current that has to cross between planes isn't a good thing for
> RFI purposes.
>
> --
> D. C. Sessions
> dc.sessions@tempe.vlsi.com