Re: [SI-LIST] : Decoupling:routing

Tom Zimmerman (tzimmer@fnal.gov)
Wed, 29 Apr 1998 09:12:19 -0500 (CDT)

> For a better description than I could write...
>
> http://www.sigcon.com/news/2_3.htm
>
> - Scott
>
>
> DFONTANE wrote:
> > I have been looking at several PWB designs and have noticed that the
> > decoupling capacitors are placed near the power pins of the IC's.
> > However, the caps are not routed directly to the power pins. The
> > decoupling caps have a via connection to the power plane or ground
> > plane.
>

I looked at this website and read the newsletter entitled "BYPASS CAPACITOR
LAYOUT." I then wrote a response to Dr. Johnson which is copied below:

Dr. Johnson,

I would like to make a few comments and relate some observations about
the subject of BYPASS CAPACITOR LAYOUT in one of your online newsletters.

You recommended that instead of the chip pwr/gnd pins being routed first
to the cap, then the cap being routed to the planes, the preferred way
would be to route the IC pins to the planes, and the nearby bypass cap
to the planes. I agree that this
configuration would seem to minimize the inductance seen by the IC and
therefore minimize ground/power bounce. However, let me relate an experience
we had in which we decided not to do it that way.

We have a mixed signal chip: a chip with a noisy digital section powered
by digital
supply DVDD/DGND, and a sensitive analog section, powered by analog
supply AVDD/AGND. The board on which the chip is mounted has one ground
plane, to which both DGND and AGND are referred. As on an ADC, both
grounds must be referred to one "system ground." The AVDD analog supply
is bypassed to the ground plane close to the chip.
Our question was: how to connect the digital supply wires and bypass
cap?? What we found was that if we connected the DGND chip pin directly
to the ground plane, and
then connected the digital bypass cap to the ground plane, the digital
supply transients then all flowed in the ground plane. Since no ground
plane is perfect, the ground plane currents caused small potential
differences across the plane, and digital noise then coupled directly
into the AVDD analog supply through the analog bypass cap, since that
cap is connected to the ground plane. The amount of noise coupling
wasn't huge, but it was enough to mess up the analog section. Then we
decided to try another method, namely connecting the DGND/DVDD pins of
the chip directly to the digital bypass cap, THEN referencing the cap
ground pad to the ground plane. In this case, much of the digital
transient current flows only in the loop containing the cap, and NOT in
the ground plane! This resulted in a cleaner system ground reference.
The difference in performance was quite striking.

It seems to me that by using this approach, you trade digital supply
bounce for a cleaner system ground plane. If you can tolerate a little
more bounce on your digital supply pins, wiring the bypass in this way
keeps the current off the ground plane. This would seem to be a really
important issue in mixed signal design. Any thoughts or comments on
this?

Thanks for your time,

Tom Zimmerman
Fermilab
tzimmer@fnal.gov

It would be nice to get any comments from si-list people also!