Packaging Short Course flyer

Shirley Dipert (
Fri, 31 May 1996 16:28:23 -0500


An Intensive Three-Day Short Course

with Raj Mittra, Paul Franzon, and Dale Becker

October 23-25, 1996 * San Jose, California



This three-day short course will provide an in-depth coverage of
numerous aspects of electrical modeling, simulation and design of
electronic packages.
Various design options will be discussed and the electrical issues
in package design will be identified. Detailed design procedures will be
outlined and the use of CAD/CAE tools for package layout will be described.
Techniques for electromagnetic modeling and simulation of
interconnects, multiconductor transmission lines, and discontinuities in
these lines, e.g., bends, tapers and vias, will be presented.
Methods for estimating the power and ground plane noise and
spurious radiation from the package will also be discussed.

Paul Franzon is an associate professor in the Department of Electrical and
Computer Engineering at North Carolina State University. He has over eight
years experience in electronic systems design and design methodology
research and development including working at AT&T Bell Laboratories and as
the founding member of a communications company. Dr. Franzon's current
research interests focus on the design sciences/methodology for high-speed
packaging and interconnect, and also for high-speed and low-power chip
design. He is a consultant to a number of companies in these areas and has
extensive experience in teaching related professional courses.

Raj Mittra is currently a professor of Electrical Engineering and the
Director of the Electromagnetic Communication Laboratory at the University
of Illinois. Beginning in August, 1996, he will move to a similar position
at Penn State University in State College, where he will also be associated
with the Applied Research Laboratory as a Senior Research Scientist. He has
directed many short courses on computational electromagnetics and
electronic packaging, both in the U.S. and in Europe, and has offered
on-site seminar series at several industrial locations including GTE
Network Systems, Cray Research, DEC, IBM and Intel. He has authored and
co-authored over 400 research papers and 20 books or book chapters. He has
served the IEEE AP-S Society as a National Distinguished Lecturer, as
President, and as an Editor of the IEEE Transactions on Antennas and
Propagation. In 1996, he was appointed a Life Fellow of the IEEE. In
addition to his University position, he also heads RM Associates, a company
that provides consulting services to many government and industrial

Dale Becker is an Advisory Engineer in the System 390 Division of IBM in
Poughkeepsie, NY. He is responsible for the electrical design of the MCMs,
SCMs, boards and cards that are used in IBM's mainframe computers. He has
fourteen years experience applying electromagnetic numerical methods to the
issues of signal integrity and simultaneous switching noise in electronic
packaging. Dr. Becker's current interests are the electrical modeling of
packaged CMOS chips in a computer system environment, and the laboratory
verification of the models and the modeling approaches.

Overview of package alternatives
=AE Mixed signal
=AE Chip Scale Packages
Review of digital circuits, DC and AC properties
=AE IBIS models and modeling
Review of synchronous design
=AE Advantages of synchronous design
=AE Signal integrity
=AE Asynchronous design (in particular clock lines)
Electrical phenomena important in packaging
=AE Reflection Noise, Crosstalk Noise and Simultaneous Switching Noise
=AE Understanding of analysis and phenomena
=AE Choosing modeling approach
=AE Solution strategies
=AE Net topologies and terminations
=AE Circuit approaches
=AE Package design, decoupling design, etc.
=AE Tie-in with measurement
System design of packaging (decision making)
=AE Basic technology mix to optimize electrical performance
=AE Interconnection cross- section (`stackup')
=AE Connections (single chip package, bare chip, connector)
=AE SSN control approach
=AE Noise budget
=AE Floorplan
Detailed design of packaging (decision making)
=AE Net topology selection
=AE Driver and other active circuit selection to optimize timing desig=
=AE Termination selection
=AE Use of CAE/CAD tools in turning a logic/timing design into a layou=
(placement and routing) that meets timing and signal integrity requirements
Package Modeling and Simulation Techniques
=AE Introduction --Signal integrity, delay, clock skew, crosstalk
noise, power plane noise, spurious radiation
Review of fundamentals of electrostatics, magnetostatics and electromagnetic=
=AE Electric field; electrostatic potential; Gauss's Law; Laplace's an=
Poisson's equations; Green's function; capacitance; multi-capacitance
systems; dielectric material; quasistatic approximation
=AE Biot-Savart law; Ampere's law; inductance
=AE Maxwell's equations; constitutive relations; polarization;
radiation integral; mutual coupling; EM interference and EM compatibility
Package modeling techniques
=AE Method of moments and the boundary element method; application to
capacitance and inductance calculations for single and multiple lines;
three-dimensional inductance and capacitance calculations; relation to PEEC
approach; examples
=AE Introduction to finite element method (FEM); application to
capacitance and inductance calculations for uniform and multiple lines with
etches of arbitrary cross-section; extension to three-dimensional
calculations of complex geometries; examples
=AE Introduction to Finite Difference Time Domain (FDTD) algorithm;
modeling of arbitrary structures including transmission lines,
discontinuities, e.g., bends, vias and backplane connectors; examples
=AE Extraction of equivalent circuits of discontinuities for insertion
into SPICE and SPICE-type circuit simulation algorithms
=AE Comparison between various modeling approaches
=AE Brief descriptions of available computer codes
Power plane noise modeling
=AE Electrical modeling of single and multilayer power planes
=AE Computation of Leff and equivalent capacitance of power planes
=AE Application to the estimation of delta-I noise
Spurious radiation from packages
=AE Techniques for calculating the current distribution on conducting
etches on PC boards
=AE Computation of spurious radiation from these currents
=AE Design recommendations
Transmission line analysis
=AE Transmission-line equations
=AE Time and frequency-domain solutions
Coupled line analysis
=AE Telegraphers equations for coupled lines
=AE Even and odd mode analysis
=AE Solution and coupling of modes
N-line analysis
=AE Matrix telegrapher's equations
=AE Eigen analysis
=AE Modal solutions and examples
Case Examples
Power distribution modeling and simultaneous switching noise
=AE Detailed example of a packaged CMOS chip illustrates creating a
model from the design drawings and using it in a circuit simulation.
=AE Approach for a complete power distribution model.
=AE Choice of appropriate electromagnetic tools.
=AE Partitioning the problem to enable the use of modeling tools.
=AE Using the model to determine the power distribution noise and
impedance across the frequency spectrum.
=AE Using the model to assist in power distribution design including
decoupling capacitor use and placement.
Signal distribution modeling and simulation
=AE Modeling signal interconnects for the prediction of delay,
reflection, and crosstalk.
=AE Deciding when full-wave tools are necessary.
=AE Assembling and using the equivalent circuit models.
System design considerations
=AE Total noise: The superposition of simultaneous switching,
crosstalk, and reflection noise.
=AE Determining the noise immunity of receiving circuits.
=AE Constraining placement of traces and switching circuits to reduce
worst case noise amplitudes.
=AE Automated verification to ensure that design constraints are met,
and noise margins are not exceeded.
=AE Validation of models and circuit simulations via measurements.


To register: Early registration is advised. Complete and return the
Registration Form or phone the registrar, Kelly Brown, at 407-892-6146 or
=46AX 407-892-0406. For technical information telephone Raj Mittra at
217-333-1202 or FAX 217-333-8986 or e-mail:;
Paul Franzon at 919-515-7351 or e-mail:; Dale Becker at
914-435-6735 or e-mail: wbecker@VNET.IBM.COM. Attendance is limited.
Register early to guarantee your course materials.

=46ee: The registration fee is $950.00 for the course. This fee includes al=
course materials and refreshment breaks and luncheons.

Schedule: Registration and check-in will be from 8:30 a.m. - 9:00 a.m. on
the first day. The seminar hours will be 9:00 a.m. - 12:00 noon and 1:30
p.m. - 4:30 p.m. each day.

Location: The course will be held at the Radisson Hotel, 1471 North Fourth
Street, San Jose, CA 95112. The telephone number is 408-452-0200.

Lodging: If you need overnight accommodations, contact the Radisson Hotel,
1471 North Fourth Street, San Jose, CA 95112, 408-452-0200. Be sure to
mention that you are attending the "Electrical Modeling, Simulation, and
Design of Electronic Packages" course to receive the special conference
rate of $112.00 per night for a single room. Reserve your room before
September 22, 1996, to be guaranteed the special conference rate.

Continuing Education Units: This program will be assigned 4 Continuing
Education Units (CEU's). A certificate of course completion will be

Substitutions and Refunds: Substitutions may be made at any time. If for
any reason whatsoever you cannot attend, the entire tuition fee, minus
$25.00 administration fee, will be refunded if cancellation is received
before start date of the course. Please register early.

In-house program: This program is also available for on-site
presentations. If you are interested in a tailor-made program to be
offered at your company site, call Raj Mittra at 217-333-1202 for further


Electrical Modeling, Simulation And Design Of Electronic Packages
October 23-25, 1996 * San Jose, California

REGISTRATION FORM Attendance is limited. Please register early.

Last Name (Please Print) First Name Middle Initial

Institution/Organization Title/Position


City State Zip + 4

Area Code Home Phone Area Code Business Phone Fax

Check appropriate item: Make checks payable to: Return this form to:

NCEE (Packaging Course) NCEE
Central Florida Facility - Management Office
1101 Massachusetts Avenue
St. Cloud, FL 34769
Attention: Registrar's Office; Kelly Brown, Registrar
Phone: 407-892-6146; FAX: 407-892-0406

____ $950.00 registration fee enclosed

____ Bill me/my organization
(Billing authorization enclosed)

____ Purchase order enclosed

In the cookies of life -- friends are the chocolate chips!
Shirley A. Dipert, CPS
Administrative Secretary
Electromagnetics & Electromagnetic Communication Laboratories
ECE Department, M/C 702 Tel: 217-333-1200
University of Illinois FAX: 217-333-5962 or 333-7427
1406 West Green Street e-mail:
Urbana, IL 61801-2991