RE: [SI-LIST] : Clock tree

Mellitz, Richard (richard.mellitz@intel.com)
Thu, 6 Aug 1998 12:48:57 -0700

Typically you need to account for the increased skew due to added
capacitance and the characteristic S shape on the edge. To do this you need
to know the clock trip points. Then you need to look at the schmoo of timing
that results for PVT* variation. Effectively skew in the two clock load case
is more sensitive to process variations but may be acceptable once you
determine sensitivities.

*PVT= process voltage temperature

... Rich Mellitz
Intel

-----Original Message-----
From: Scott McMorrow [mailto:scottmc@teleport.com]
Sent: Thursday, August 06, 1998 3:30 PM
To: Shimon_Turgeman@amat.com
Cc: si-list@silab.Eng.Sun.COM
Subject: Re: [SI-LIST] : Clock tree

Shimon,

Close in the signal integrity world is one fifth to one sixth
of the fastest signal rise and/or fall time. If the distance
from the loads to the T junction is less than this, then there will
generally be minimal effect due to reflections.

However, the clock receiver input capacitance and package
parasitics also factor into the analysis. At high edge rates,
the package and die capacitance can be a significant factor.
Don't try to route clock trees without prior simulation, especially
to dissimilar receivers. You may end up with a rude surprise, otherwise,
in production.

Regards,

Scott

Shimon_Turgeman@amat.com wrote:

> is any one build clock tree on large board.
>
> what is the best way to build the clock tree ?
> I connect the same clock to few consumers which are very close ? is that
> O.K ? what is consider as "close" ?
> what is the best termination and connection for that ?
>
> Best regards
> Shimon Turgeman
> ISRAEL

--
___________________________
Scott McMorrow
Principal Engineer
SiQual

mailto:scottmc@siqual.com ___________________________