Re: [SI-LIST] : SI openings at Stratus -- ... last one

Kazi Hassan (khassan@pakhi)
Fri, 13 Feb 1998 02:24:46 -0800

Personally I like job opportunity postings. It's not because I
am looking for a job, but it gives me an idea about what people
are doing ( apparent from their job requirements ), what tools
& methods are being used etc. etc. After reading a lot of job
postings I can confidently say, for example, what are the most
popular SI tools being used in the industry, among other things.

Thanks,
Kazi
Sun Microsystems

> From fyuan@qdt.com Thu Feb 12 18:20:11 1998
> Date: Thu, 12 Feb 1998 17:43:29 -0800
> From: Frank Yuan <fyuan@qdt.com>
> Organization: Viewlogic Systems Group, Synopsys, Inc.
> X-Mailer: Mozilla 3.01Gold (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Murali Raj <muralir@ipg.3com.com>
> Cc: Prasad Modali - Katmai Design <pmodali@pcocd2.intel.com>,
> si-list@silab.Eng.Sun.COM, Steve_Mango@stratus.com
> Subject: Re: [SI-LIST] : SI openings at Stratus -- ... last one
> Content-Transfer-Encoding: 7bit
> Sender: owner-si-list@silab.Eng.Sun.COM
>
> A healthy exchange of technical information as well as
> professional oportunity by practice SI engineers is a
> very positive thing on the SI-list. Personally I done't
> mind Steve's posting except it's a little long.
>
> Murali Raj wrote:
>
> > As another responder suggested, the signal-to-noise
> > ratio apparently is very high on this list
> > which permits tolerance for such messages.
> >
> > While I apologize for my comments due to lack of
> > exposure to the group, I still believe it is
> > unwise to use this forum for anything other than
> > what its original intent was.
> >
>
> I am sorry, but I think your response is so far the loudest
> noise on this list I have heared... Attack other SI'ers do
> not create friendly envirornment, but can only make more
> noises and "bad name" to this list. If you are new to SI-list,
> please "using ethical means" in communicate with others.
>
> Frank
>
>
> > On Thu, 12 Feb 1998, Prasad Modali - Katmai Design wrote:
> >
> > -->
> > -->Sorry, but I do not understand what is so outrageous about Steve's posting.
> > -->People have done this before and I do not remember seeing such a caustic
> > -->response...I'd just ignore it...
> > -->
> > -->Earlier, Murali Raj writes:
> > -->[Charset unsupported, skipping...]
> > -->
> > --> This is absolutely outrageous.
> > --> I strongly object to this.
> > -->
> > --> Please do not make spoil the sanctity
> > --> of a group to which people sign on for
> > --> information and knowledge exchange.
> > --> Not for receiving, as you very mildly put it,
> > --> "junk mail".
> > -->
> > --> Its people like you who give the web a bad name.
> > -->
> > --> I hope you desist from such activities in the future
> > --> and start using ethical means of finding people
> > --> to work in your organization.
> > -->
> > -->
> > -->
> > -->
> > -->On Thu, 12 Feb 1998 Steve_Mango@stratus.com wrote:
> > -->
> > -->-->
> > -->-->Sorry for the "junk" mail... but if any of you signal fidelity engineers
> > -->-->are available... please read on:
> > -->-->
> > -->-->====
> > -->-->
> > -->-->My name is Steve Mango and I am the hiring manager of the Analog and
> > -->-->Signal Fidelity Group at Stratus (a fault tolerant computer design
> > -->-->company) in Marlboro, Ma. I have openings for signal fidelity engineers
> > -->-->to join my fast-growing team. I would prefer full time permanent
> > -->-->engineers, but I am willing to consider contractors.
> > -->-->
> > -->-->My group must solve many high-speed technical challenges as we push
> > -->-->clock and bus speeds >100MHz. I am looking for experienced signal
> > -->Press any key to return to index.my group. [Note: These positions are for
> > -->-->USERS of signal fidelity tools to solve complex problems, rather than
> > -->-->for software developers of new software analysis tools.]
> > -->-->
> > -->-->* Help define/diagnose/solve complex signal fidelity problems (clock
> > -->-->generation/distribution, interconnect design, timing, termination,
> > -->-->decoupling, power/ground distribution, package/connector selection,
> > -->-->etc.).
> > -->-->
> > -->-->* You should have at least 3-5 years experience in the signal fidelity
> > -->-->and high speed digital design field.
> > -->-->
> > -->-->* You should have hands-on experience with modeling and simulating with
> > -->-->Quad Design tools (MOTIVE, XTK, TLC), SPICE (PSPICE and HSPICE),
> > -->-->electromagnetic field solvers (e.g., Greenfield, Pacific Numerix,
> > -->-->Maxwell 3D, etc). Candidate should be familiar with high speed board
> > -->-->interconnect routers (Allegro and CCT router preferred). Experience with
> > -->-->IBIS modeling and Interconnectix software is a major plus. Candidate
> > -->-->should also be familiar with high speed test plan development, test
> > -->-->measurements techniques and lab equipment (HP and Tektronix). Experience
> > -->-->with current high speed processors and multiple logic families is
> > -->-->desirable. Other pluses are experience with custom ASIC cell design,
> > -->-->phase lock loops, hot plug, FET switches, PCI Bus, SCSI bus, and
> > -->-->web-based documentation.
> > -->-->
> > -->-->M-7 Education: BS degree minimum.
> > -->-->
> > -->-->ItM-^Rs an exciting time here at Stratus
> > -->-->
> > -->-->Come Join our team.
> > -->-->
> > -->-->Please call me at (508) 490-6231
> > -->-->Or email me at: Steve_Mango@stratus.com
> > -->-->
> > -->-->
> > -->
> > -->
>