Re: Power/ground connections/bypassing on ICs

Don Abernathey (dla@pyramid.com)
Mon, 28 Apr 1997 14:45:47 -0700

Power and ground connections seem to be dictated by layout concerns
and soldering concerns. E.g. a BGA and an SOIC use different pad to
via connection techniques, the BGA using a short (xxxmil) trace to via
or sometimes pad-in-via, and the SOIC using a pin-escape (short, fat
trace).

Assuming for a moment that pad-in-via yields the lowest inductance
connection, I can tell you that I have never seen pad-in-via done on
an SOIC footprint. Why? Because it is harder to solder. I believe that
short-trace-to-via (dog bone) and pad-in-via are done in BGAs
primarily because they are the most cost-effective (mainstream) method
of high-density soldering, with dog bones seemingly more popular than
pad-in-via.

These are correct tradeoffs since the mainstream applications for our
technology are cost driven. Volume, mainstream manufacturing technology
is more important than engineering performance. Design
it once but build a zillion. It could be that a few less DPM (solder
joints) is worth more than a few extra millivolts of noise margin.

I have used long, thin microstrip traces (pad layers) and a couple
0805 SMT caps to make an analog filter for an ethernet chip. But to
tell the truth it was a shot in the dark. I knew the value of the
inductances and capacitances and SPICE told me the behavior of the
network over frequency, but I had no clue what the interaction with
the ethernet chip would be. But this was also a fairly safe design
since the Bit Error Rate of ethernet is something that few folks would
notice unless it is grossly bad.

I have also had IC vendors write app-notes dictating the use of
ferrite beads and split planes without providing one shred of evidence
that it was necessary, but only the words "good analog design
practice"- yeah right. No design target.

I believe in low-impedance connections for bypassing, high-impedance
for filtering and split planes when I want to make sure that I know
where currents are flowing. About the only thing that is accomplished
by mixing filtering with the bypassing is to slow the edge rate -
great if that is what you want to do.

*************************
Thank you |
Don Abernathey |
(503)690-6234 |
dla@pyramid.com |
*************************

On Apr 28, 11:40am, Andy Ingraham wrote:
> Subject: Power/ground connections/bypassing on ICs
> I am tempted to open, once again, the discussion about how to connect
> power and ground pins to ICs on a multi-layer PCB, and how best to
> bypass them.
>
> I have held the firm belief that IC power and ground pins should
> always be tied right to their planes as soon as possible, with the
> shortest trace lengths. Then bypass capacitors can be added near
> those pins.
>
> Some have suggested the alternative of bringing power and ground from
> the planes, first to the bypass capacitor, and then to the IC pins,
> something like this:
>
> +----------+
> ###| |###
> | |
> ###| |###
> vias | |
> X=====###========###| |###
> | | | |
> X=====###========###| |###
> bypass | |
> capacitor ###| |###
> +----------+
> I.C.
>
> I feel this is dangerous because of the added inductance. The
> power/ground planes are your best high frequency bypass capacitor
> (although a small one), so I'd think you want to get your IC pins
> brought to them as quickly as possible, without wasting etch going to
> a discrete capacitor which may not be very effective anyway if it's
> above self resonance. Also the power and ground pin inductance is
> effectively in series with all output drivers when they switch. So
> I avoid this technique.
>
> But I recently had a short discussion with an engineer who promoted
> the latter, and insisted it was better in mixed-signal environments.
> Most of my work has been straight digital lately, though I do find
> myself surrounded by a smattering of mixed-signal components for such
> things as ethernet.
>
> The presumed justification is that these mixed-signal devices benefit
> from the additional small filtering provided by the trace inductance.
>
> By the way, the IC under discussion had all digital inputs and
> outputs, but some internal clock re-timing, and no vendor
> recommendations regarding power filtering.
>
> Does it make sense to do this? Do I want to adopt a strategy of using
> the first method for straight digital devices, and the second method
> for mixed-signal devices that don't use filtered power?
>
> Is it wise to do this with both power and ground leads? Or should
> ground pins always route directly to the ground plane, with longer
> traces in only the power leads? (Assuming no PECL, of course.)
>
> Thanks for advice.
> Regards,
> Andy Ingraham
>-- End of excerpt from Andy Ingraham