[Fwd: Interfacing Sync DRAMs]

Danwei Xue (danwei@pico.apple.com)
Wed, 04 Jun 1997 10:47:40 -0700

--------------167EB0E72781E494446B9B3D
Content-Type: text/plain; charset="us-ascii"
X-Sun-Content-Length: 389

Hi, Eitan,

Thank you very much for your information.

For LVTTL, you can point your web browser at

http://global.ihs.com

Click United States (as I did), then Search for "Low Voltage TTL" in the
Title Contains field.

For other questions, I am forwarding your e-mail to the SI list server
so that some specialists there may give you answers.

Best wishes,

Danwei
Apple Computer, Inc.

--------------167EB0E72781E494446B9B3D
Content-Type: message/rfc822; charset="us-ascii"
Content-Disposition: inline
X-Sun-Content-Length: 2253

Return-Path: <eitan@galileo.co.il>
Received: from scv1.apple.com (A17-128-100-139.apple.com) by pico.apple.com (4.1/SMI-4.1)
id AA05201; Wed, 4 Jun 97 04:48:25 PDT
Received: from mail-in2.apple.com (mail-in2.apple.com [17.254.0.58])
by scv1.apple.com (8.8.5/8.8.5) with ESMTP id EAA24460
for <danwei@pico.apple.com>; Wed, 4 Jun 1997 04:47:31 -0700
Received: from galileo21.galileo.co.il (galileo21.galileo.co.il [192.116.246.22])
by mail-in2.apple.com (8.8.5/8.8.5) with ESMTP id EAA24744
for <danwei@pico.apple.com>; Wed, 4 Jun 1997 04:45:17 -0700
Received: from pc13 (pc13.galileo.co.il [192.116.246.249])
by galileo.co.il (8.8.5/8.8.5) with SMTP id OAA18646
for <danwei@pico.apple.com>; Wed, 4 Jun 1997 14:47:56 +0200 (IST)
Message-Id: <199706041247.OAA18646@galileo.co.il>
Comments: Authenticated sender is <eitan@galileo21>
From: "Eitan Medina" <eitan@galileo.co.il>
Organization: Galileo Technology Ltd.
To: Danwei Xue <danwei@pico.apple.com>
Date: Wed, 4 Jun 1997 13:45:01 +0200
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7BIT
Subject: Interfacing Sync DRAMs
Return-Receipt-To: "Eitan Medina" <eitan@galileo.co.il>
Priority: normal
X-Mailer: Pegasus Mail for Windows (v2.33)

Hi Danwei,

Hope you found my last mail helpful.

Do you have pointers to material on LVTTL and T-LVTTL ?
My 3.3V ASIC CMOS library for pads support TTL signalling.

Questions I am looking for:
What is the point where TTL signalling is not enough ?

Using a standard CMOS 3.3V ACIS library, can I interface
directly to high speed SDRAMs (125/100Mhz) ?

Assuming that the SDRAM and my device are close together
on the same board - would TTL levels be enough ? If not,
I need to define what changes in the library I need...

What is LVTTL and T-LVTTL exactly ?
Are there applicatione-notes you know of on this.

The next step is figuring all this about SSTL.

Thank you,

Eitan

Eitan Medina
Email: eitan@galileo.co.il
Galileo Technology Ltd.
15 Geron st.
P.O.Box 2786
Yehud 56217
ISRAEL
Tel: +972-3-6320220
Fax: +972-3-6320221
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
* check out our new web site: http://www.GalileoT.com *
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

--------------167EB0E72781E494446B9B3D--