[Fwd: Interfacing Sync DRAMs]

Danwei Xue ([email protected])
Wed, 04 Jun 1997 10:47:40 -0700

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Hi, Eitan,

Thank you very much for your information.

For LVTTL, you can point your web browser at


Click United States (as I did), then Search for "Low Voltage TTL" in the
Title Contains field.

For other questions, I am forwarding your e-mail to the SI list server
so that some specialists there may give you answers.

Best wishes,

Apple Computer, Inc.

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From: "Eitan Medina" <[email protected]>
Organization: Galileo Technology Ltd.
To: Danwei Xue <[email protected]>
Date: Wed, 4 Jun 1997 13:45:01 +0200
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Subject: Interfacing Sync DRAMs
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Hi Danwei,

Hope you found my last mail helpful.

Do you have pointers to material on LVTTL and T-LVTTL ?
My 3.3V ASIC CMOS library for pads support TTL signalling.

Questions I am looking for:
What is the point where TTL signalling is not enough ?

Using a standard CMOS 3.3V ACIS library, can I interface
directly to high speed SDRAMs (125/100Mhz) ?

Assuming that the SDRAM and my device are close together
on the same board - would TTL levels be enough ? If not,
I need to define what changes in the library I need...

What is LVTTL and T-LVTTL exactly ?
Are there applicatione-notes you know of on this.

The next step is figuring all this about SSTL.

Thank you,


Eitan Medina
Email: [email protected]
Galileo Technology Ltd.
15 Geron st.
P.O.Box 2786
Yehud 56217
Tel: +972-3-6320220
Fax: +972-3-6320221
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