RE: [SI-LIST] : Excessive clock overshoot

Muranyi, Arpad ([email protected])
Thu, 14 May 1998 08:13:00 -0700


Even though Charles is correct, the problem is not so much the high speed
stength, in my opinion. If I remember correctly, these devices use
pullups which have a very high impedance above a transistor threshold
below the high rail (~3.5-4.0 volts for a 5 volt device). This high
and the lack of clamping diodes (or clamping circuits) results in an open
transmission line, which allows the reflections to double the amplitude.

Use fast and strong devices if you need the speed, but make sure your lines
properly terminated (clamped).



I have seen this many times before with FCT logic. In my experience it is
the worst choice of logic families from a signal integrity point of view.
The edge speed is very fast, and current drive is very high, and so the
speed is fast---but that is bad for signal integrity. I suggest you try
ABT, or F. There is also other types of FCT which are intended to be more
"SI friendly".

Charles Hill, consultant
[email protected]

From: fabrizio
zanella[SMTP:fabrizio=zanella%eng%[email protected]]
Reply To: fabrizio=zanella%eng%[email protected]
Sent: Wednesday, May 13, 1998 2:16 PM
To: [email protected]
Subject: [SI-LIST] : Excessive clock overshoot

I have a question regarding an FCT clock (TTL levels) driving a heavily
loaded backplane. On the driver pin we see excessive overshoot on the L-H
transition which increases as we increase the clock frequency. This
overshoot goes from 5V at 33MHz to 6.5-7.0V at 45MHz. The stub impedance
is 75 ohms, backplane impedance 25 ohms loaded. There is a clamping diode
on the H-L side but not on the L-H. The H-L side does not have any
I have asked the manufacturer and they have never seen this phenomena, nor
do they have an explanation for it.
Any ideas on what could be causing this?

thanks and regards,
Fabrizio Zanella
Design Engineer
EMC Corporation
[email protected]