Re: [SI-LIST] : Driver Strength

chong lin ([email protected])
Mon, 9 Mar 1998 09:00:38 -0800

Are there CAD/EDA tools that can analyze/simulate the need of the questio=
raised here ?

Any one ?


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-----Original Message-----
From: Bernardino Le=F3n <[email protected]>
To: [email protected] <[email protected]>; [email protected]=
<[email protected]>
Date: Monday, March 09, 1998 3:47 AM
Subject: Re: [SI-LIST] : Driver Strength

>D. C. Sessions wrote:
>> Lfresearch wrote:
>> > the discussion on driver strength has prompted me to make an
>> observation seen
>> > during EMC testing. One of the immunity tests fires rapid ( ns
>> timeframe )
>> > voltage transients onto all the wiring interfaces. I have observed
>> that when
>> > digital circuits respond to the transients, it is the devices with
>> the weakest
>> > pull-up or pull-down that go first. By reversing the transient
>> polarity,
>> > significant shifts in the level at which the circuit responds may be
>> observed.
>> > Also, if the pulling circuit is not located close to the input pin,
>> the trace
>> > isolates its effect somewhat.
>> Just to make sure: are you talking about logic upset or hard failure?
>> Most CMOS outputs have the same number of drains connected to the
>> pad regardless, but adjust strength by tieing off gates to keep the
>> devices OFF all the time. That way, ESD transients still have the
>> full device complement to share the energy.
>> For logic upsets, OTOH, the problem is that current into a
>> high-impedance
>> output will produce higher voltage responses than current into a
>> low-impedance
>> output (Duh!)
>> > The problem is that by using drivers with lower drive capability we
>> end up
>> > with designs that could have immunity problems. However, devices
>> with higher
>> > drive capability tend to be the cause of radiated emissions
>> problems.
>> >
>> > I guess there needs to be middle ground ( from the EMC engineers
>> point of view
>> > ), so that we can maximise immunity and minimise emissions. Anyone
>> want to
>> > take a shot at a set of guidelines?
>> Well, the EMC problem isn't so much driver strength as Ldi/dt noise.
>> This can
>> be addressed by:
>> 1) Reducing max I independently of dt and L (the weak driver approach)
>> 2) Reducing L independently of dt and max I (packaging solutions)
>> 3) Increasing dt independently of max I and L (custom drivers)
>> 4) Isolating the supply paths for high-speed I/O from victim lines
>> (floorplanning)
>> As is almost always the case in EMI/susceptibility engineering a
>> combination approach works best. Drivers with no more static drive
>> than necessary should be used with predrivers as slow as the
>> application
>> will stand, with lots of low-inductance supply connections split
>> between
>> noise generating and noise susceptible I/O groups.
>> --
>> D. C. Sessions
>> [email protected]