A couple of things to consider, however:
Most such ICs employ separate VSS and VDD pins for internal (logic)
and external (I/O) power rings, even if the supply voltages are the
same. Thus, the noise tends to be kept separate through the IC
package; so as long as PCB supply bypassing is sufficient, and
depending on the design of the package, it may be OK to handle SSO
noise in the usual way (adding up outputs that switch). At least
for first order.
The intrinsic (on-chip) capacitance of the internal logic voltage rail
tends to be big (much larger than that of the I/O voltage rails),
helping to sink much of the noise and even out the current pulses on
the internal logic VSS/VDD pins.
I may be mistaken, but I think some of the published papers on
DIGITAL's Alpha CPU chips have touched on the internal noise
especially from the huge clock buffers.
Yes, don't forget those clamping diode currents!