Re: [SI-LIST] : Output Impedance

D. C. Sessions (dc.sessions@tempe.vlsi.com)
Thu, 2 Apr 1998 08:29:58 -0700

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Brian Young wrote:
>
> I'm convinced IBIS works great if you have no rail collapse so that the IV
> curves are valid. I don't think they are valid under heavy bus switching
> with significant rail collapse, although I hear people claim otherwise. I
> just don't see how IV curves provided at, say 3.3V, work when you have 0.5V
> of collapse. Any comments?

Almost always correct. For normal CMOS outputs, rail collapse steals
gate
drive and thus violates the assumptions used in creating the IBIS model
in
the first place. The only exception I know of is N-follower pullups,
where the gate drive gets stronger as the rails drop. Combined with a
regular P pullup this can be pretty much Vddq independent. (Doesn't
help
with the pulldown, though.)

It's been suggested that semiconductor manufactureres (you and me,
Brian)
produce worst-case models that take into account SSO collapse. This
isn't
easy in IBIS as it stands because it involves multiple chip models for
different conditions. If anyone has an inspiration on a way to extend
IBIS to make this easier, by all means forward it to the IBIS forum:
mailto:ibis@eda.org

> > ... I have compared the results of IBIS simulation to that of full
> > HSPICE model simulation and hardware measurements for several different
> > transmission line problems. IBIS model simulation compares very well to
> > both.

Certainly within the envelopes of device, dielectric, geometric,
etc. tolerances.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com