It seems there are several mechanisms that interact to be concerned with.
1. The PLL jitter has a frequency dependent sensitivity to supply voltage
noise.
2. The PCB and its bypassing has a frequency dependent impedance.
3. The offending threat has a frequency dependent power and impedance
level.
The power to ground plane impedance including bypass capacitors should look
like a very low impedance transmission line with voltage maxima on the
edges of the PCB. For a given frequency, the impedance varies with
position. The impedance also varies with frequency. The offending theat
couples power into the PCB power and ground depending on position and
frequency. Similarly, the PLL victim receives noise from the PCB power and
ground depending on position and frequency.
You might try modelling the threat as an injected current between PCB power
and ground. Terminate your power amplifier in 50 ohms, then connect a
resistor to the power (say 200-1000 ohms). The actual noise injected is
the aggregate of the threat output impedance, input impedance of the PCB
power, and transfer function to the PLL.
The PLL probably has a digital phase detector so it has a wide input noise
bandwidth--noise can alias into the loop bandwidth of the PLL since it is a
sampled system, plus gates have a fast response thus a wide BW. The VCO
frequency determining mechanism is probably not high Q (not LC tank or
crystal) so VCO power supply reject is important.
Sounds like an interesting investigation---good luck.
Chuck Hill, consultant
[email protected]
----------
From: Ray Anderson[SMTP:[email protected]]
Reply To: Ray Anderson
Sent: Tuesday, September 29, 1998 10:51 AM
To: [email protected]
Subject: [SI-LIST] : Conducted EMC Testing of PLL jitter
Perhaps some of the EMI/EMC savvy people on the list have
some comments and/or opinions on how best to couple an interfering
RF signal into the power planes of a digital board to accomplish
some EMC testing.
Basically I have a system (CPU's, memory, PLL's etc.) that
runs at a clock rate of several hundred MHz. I need to do
some tests to evaluate what effect noise on the power planes
over the range of ~DC to 1GHz has on the PLL jitter.
I would like to inject a signal (in the range of ~DC to 1 GHz)
into the power planes (up to maybe 200 mv p-p amplitude) to
see how the PLL handles the noise on it's power feed.
I have a broadband (10KHz to 1GHz) amplifier that can provide
an excitation level of up to 20 watts into 50 ohms.
We believe the system power distribution system (planes, bypass
caps etc.) looks like a broadband 50 milliohm (or less) impedance.
The question is: would impedance matching the 50 ohm amplifier
impedance to the sub-ohm plane impedance by means of a broadband
ferrite transmission line transformer be a prudent thing to do,
or is there another accepted way of doing this?
Any comments or suggestions on alternate ways of evaluating the
jitter performance of a system PLL in response to power supply
noise over a wide bandwidth would be of interest.
Ray Anderson
Sun Microsystems Inc.
[email protected]
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