Re: [SI-LIST] : Split vs. common chip busses

Mike Degerstrom (
Mon, 13 Jul 1998 12:41:46 -0500


Thanks for your reply. Please find my comments below:

On Jul 10, 2:41pm, D. C. Sessions wrote:
> Subject: Re: [SI-LIST] : Split vs. common chip busses
> Mike Degerstrom wrote:
> >
> > Fellow si-listers:
> >
> > Presently we have a CMOS ASIC design with VDD and VSS supplies
> > for the core logic and separate VDD and VSS supplies for
> > the I/O. I believe that historically the use of separate
> > supplies for the core and I/O was to keep the noisy I/O
> > supplies isolated from the core supplies.
> >
> > Has anyone analyzed the problem to determine the benefit
> > or harm that would occur from using common VDD and VSS
> > supplies for both core and I/O - specifically as it
> > applies to today's submicron/million+ gate ASICs? Any
> > designs out there that worked with common supplies
> > to core and I/O?
> >
> > We are presently evaluating a package that will have low
> > inductance VSS path but a high inductance VDD path. With
> > common supplies on the chip we could use the core's VDD to VSS
> > capacitance to lower the AC impedance of the VDD supply
> > and thus reduce switching noise when switching from
> > LOW to HIGH.
> Right now we're making changes to some of our standard
> cells to isolate not only core and I/O, but predriver
> from both. The I/O noise not only messes up input
> thresholds (bad enough) but also plays Hob with PLLs
> and other analog circuitry in the core -- and few purely
> synchronous designs today *don't* have PLLs.

At some point ( I guess the predriver in your case) your
core has to talk to the I/O. So wouldn't you want
common supplies to your core and I/O so the thresholds
move together?
> The core capacitance is actually small relative to the
> I/O currents (check the numbers). Not only that, but
> a lot of the core supply-ground capacitance has a very
> high ESR, rendering it useless. Worst of all, I/O
> noise isn't vdd-vss noise, it's chip-PWB noise. SSOs
> drive asymmetrically, so any core capacitance would
> just cause both core rails to bang around together as
> the outputs switch.

My numbers are as of yet uncertain. Also, the last time
I did SI work with CMOS ASICs was well before submicron/million
gate count technologies came to be. I did measure
about .7nf in a 100K gate count array, however. Now,
I believe that there are 10's of nf core capacitance on
submicron/million gate count technologies. This
capacitance should be dominated by transistor isolation
wells. I can't speak for the ESR, but you've raised a
flag so I do need to investigate the ESR. But desiring
a .1 ns response time from your core capacitance and
having one million transistors supplying 10nf of capacitance
I believe that the well capacitance around each transistor
would have to have an ESR of less than 10 killo-ohms.

I haven't worked out how much capacitance I'll be driving,
but my goal would be to keep it less than 1/10 that of
on on-chip capacitance. I think I'm in the ball
park with this goal.

> Finally, the worst outcome for common core/ring supplies
> is that the outputs actually suck the internal supply out
> of tolerance (screwing up your timing), adds noise to edges
> (screwing up your timing even worse), or even pulling the
> supply low enough to lose state in (for instance) memories.
> --
> D. C. Sessions
>-- End of excerpt from D. C. Sessions

One detail that I left out was that I can use a continuous
ground plane through my package, but VDD has to be supplied
through traces on the signal layers just as I/O are brought
in. So my simulated VSS noise is ~.5V and VDD noise is
~1.5V for a 3.3V supply. You can see why I'd want my
VDD supply to act more like the VSS supply. If my simulations
are accurate, then I don't think my core will suffer
too much with .5V noise. You do have a point about the
PLL - so that will take more investigation. Neglecting
the mixed signal circuits, such as PLL, I have received
another posting sent to me (but not to the si-list) where
it was recommended that core and I/O share common supplies.
This recommendation was made to lower the overall inductances
and to keep core and I/O thresholds tracking together. Nothing
was said about using core capacitance for decoupling the
I/O, however.

In the past, with ECL technology and emitter follower buffers,
it probably made sense to have a separate VCC and VCCO supply.
This is because the outputs track the VCC supply and are
fairly insensitive to VCCO noise. But standard CMOS output
buffers do not behave this way.


Mike Degerstrom                       Email:	
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