[SI-LIST] : Re: delay lines with PCB traces

Michael Chin (mchin@cisco.com)
Wed, 24 Sep 1997 14:59:53 -0700

I would like to echo that this zip-zag trace pattern has been known
and oberserved in the lab to reduce the total expected delay. I
came across a situation when I was using PCB trace to add some "skew"
into the clock nets. The actual clock skew that was induced thru this
kind of topology was measured to be less than the min. expected delay
by 5% to 10%.

I ended up running the serpentine in a wider gap (24 mil to 30 mil)
to allow an accurate clock skew distribution. But, this costed us
more space on the PCB to delay the clocks.

Michael Chin
Cisco Systems, Inc

> From owner-si-list@silab.Eng.Sun.COM Wed Sep 24 14:35:44 1997
>
> The 2nd order effect that Andy alludes to is what I call current jumping
> in a zig-zag pattern. Primarily due to inductive coupling, the active
> signal induces a return current on itself which due to the zig-zag pattern
> propagates in the same direction as the active. The outcome of this effect
> is a net delay decrease.
>
> So when you force wire in a zig-zag pattern to obtain a certain net delay
> (i.e. for clock balancing, etc.) and expect a To*L result, be careful.
> You may have just added an unwanted skew in your clock distribution or
> pop up early mode surprise in your design.
>
> > ...
> > What about second-order effects; for example, does the little zig-zag
> > approach allow a weaker wave mode to zip right along as if the
> > zig-zags weren't there?
>
>