RE: [SI-LIST] : PCI Slew Rate Test Load

Farrokh Mottahedin (
Wed, 8 Apr 1998 16:11:48 -0700


My recollection from a PCI design several years ago is that PCI CMOS bus
drivers are specified in terms of their AC (rather than DC) switching
characteristics. Buffer strength is specified by an AC drive point
which defines an acceptable first step voltage, (high or low going)
together with required currents to achieve that voltage. This is
because reflected wave switching is used. To drive a transmission line,
the outputs must source or sink a minimum amount of current to insure a
large enough voltage step on the line, given the characteristic
impedance. At the same time, however, it is necessary to limit the
drive current to keep the reflected voltage wave within acceptable
limits. The minimum and maximum ac-drive curves reflect these two
considerations. There are two IV curves defined in the PCI spec, one
for pull-up and one for pull-down. Each curve displays a shaded area
defining the optimum operational area. To make a long story short, if
you determine the max and min impedance an output must drive, 500 Ohms
(two 1K resistors in parallel) is a good compromise.

Farrokh Mottahedin
Manager, Interface Eng. - Analog
Quantum Corporation
(408) 324-7934

> -----Original Message-----
> From: Chan, Michael []
> Sent: Wednesday, April 08, 1998 11:16 AM
> To: ''
> Cc: Goodrum, Alan
> Subject: [SI-LIST] : PCI Slew Rate Test Load
> Hi:
> Can anybody explains why the slew-rate test of PCI output buffer
> in PCI
> spec. 2.1 uses 1Kohms to Vcc and 1Kohms to Gnd
> in addition to 10pF cap. to Gnd ? I can understand the use of 10pF
> cap. in
> the test set-up but I cannot understand why 1Kohms
> resistors are being use? Any comment(s) are deeply appreciated.
> Regards,
> Michael Chan
> Compaq Computer Corporation
> 20555 SH249 MS090403
> Houston, TX 77070-2698
> Tel: (281)518-9189