Re: [SI-LIST] : Conducted EMC Testing of PLL jitter
Fred Balistreri (firstname.lastname@example.org)
Tue, 29 Sep 1998 12:57:27 -0700
Ray Anderson wrote:
> Perhaps some of the EMI/EMC savvy people on the list have
> some comments and/or opinions on how best to couple an interfering
> RF signal into the power planes of a digital board to accomplish
> some EMC testing.
> Basically I have a system (CPU's, memory, PLL's etc.) that
> runs at a clock rate of several hundred MHz. I need to do
> some tests to evaluate what effect noise on the power planes
> over the range of ~DC to 1GHz has on the PLL jitter.
> I would like to inject a signal (in the range of ~DC to 1 GHz)
> into the power planes (up to maybe 200 mv p-p amplitude) to
> see how the PLL handles the noise on it's power feed.
> I have a broadband (10KHz to 1GHz) amplifier that can provide
> an excitation level of up to 20 watts into 50 ohms.
> We believe the system power distribution system (planes, bypass
> caps etc.) looks like a broadband 50 milliohm (or less) impedance.
> The question is: would impedance matching the 50 ohm amplifier
> impedance to the sub-ohm plane impedance by means of a broadband
> ferrite transmission line transformer be a prudent thing to do,
> or is there another accepted way of doing this?
> Any comments or suggestions on alternate ways of evaluating the
> jitter performance of a system PLL in response to power supply
> noise over a wide bandwidth would be of interest.
> Ray Anderson
> Sun Microsystems Inc.
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Ray, I don't have any inputs as to how to measure or evaluate this
situation in the lab as its been many years since I dealt with this
sort of thing. However I'm wondering if you couldn't simulate the thing
assuming you have a spice transistor level discription of the PLL.
Behavior PLL probably won't do in this case. Its even marginal with
the spice transistors but it would be an interesting problem to model.