Several weeks ago I asked a question to the list concerning
simultaneous switching noise (SSN). I received many useful
answers. Most pointed me towards Senthinathan and Prince,
which I have ordered, but not yet received.
One issue that concerned me was the influence of load
capacitance on the SSN. The answer, it seems, depends on
the design of the output buffer:
1) If the P and N transistors are momentarily ON,
then the "through" current dominates, which means that
the maximum noise amplitude is independent of the load.
This is because the di/dt of the through current is greater
than the di/dt of any (dis-)charge current.
2) If the output buffer is designed so that the P and N
buffers are never both ON, then the SSN source
is predominately the (dis)charge current. SSN increases
with Cload up to a certain value of Cload, then plateaus
If the Cload is replaced by a transmission line, then
then a simple rule is that the SSN is (Iz/Isc)*Vmax,
where Isc is the short-circuit output current and Iz is the
output current for a resistance equal to the impedance of
This interpretation prompts the following question:
Are real-life buffers designed such that the P and N
transistors are never ON simultaneously?
-- John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09