We all know about minimizing and reducing, etc. But does anyone out there
actually DESIGN their bypassing networks? I sure don't know how to do it!
If I did, perhaps I could design a bypass network that would serve my needs
AND the needs of the assembly/manufacturing folks. A few years back, at a
SPICE class in San Jose, I heard a fellow from IBM state that he designed his
bypassing networks in the frequency domain. Anyone else doing this?
I've tried, but without satisfactory results. Any suggestions on scaling
the problem? Any ideas on how to model the timing jitter between parts
that are simultaneously switching with ~2ns edges? Are there any bypass network
designers out there? I'm sure I (at least) could use some real design help on
this one. No opinions, intuitions or hand-waving please. I have plenty of my
own and they are probably more conservative than need be.
--- Gary D. Peterson _/_/_/ _/ _/ _/ SANDIA NATIONAL LABORATORIES _/_/_/ _/ _/_/ _/ _/ P.O. Box 5800, M/S 0503 _/_/ _/_/_/ _/ _/ _/ _/ Albuquerque, NM 87185-0503 _/_/_/_/_/_/ _/ _/ _/_/ _/ Phone: (505)844-6980 _/ _/_/ _/ _/_/_/ _/ _/ _/_/_/_/ FAX: (505)844-2925 _/ _/_/ _/ E-Mail: email@example.com _/_/_/