Re: component overstress

Arthur Collard ([email protected])
Mon, 11 Mar 96 14:43:31 CST

On 11 Mar 96 15:04:28 George Stevens writes:

> I am currently investigating a phenomenon that is occuring associated with 64k
> x 4 Srams
> from Quality Semiconductor. Field failures are occuring characterized by
> component failures,
> which, when a Failure Analysis is completed by the manufacturer, finds an input
> open and
> carbon deposits observed on Vcc and ground pins. This, reportedly, indicates
> high current draw
> caused by "overstress" in our application. I am currently attempting to
> measure over/undershoot
> and voltage spike anomolies on the board but have found nothing that violates
> the manufacturers
> spec yet. I have been told that contention can also overstress an input, I
> assume when two or
> more drivers attempt to pull the input to the Sram low. Is this possible??
> Anybody have any history on this device or ideas on what other signal anomolies
> may cause an overstress
> on an input stage?

I have seen this type of problem many times it's called latchup. This can be
caused by an overstress at an input, output or I/O pin. The latching mechanism
is inherant to CMOS devices and is usually triggered by excessive voltage. Most
designs protect against +/- 7 volts and +/- 100mA static however the pulse
latchup testing is a better test.
The place where the latchup mechanism is initiated from does not necessarily
damage. The damage is usually where the latching currents flow to and from
namely power and ground metal and associated junction contacts. I put a list
together of items external and internal to the chip which would cause this to

Latch-up trigger mechanisms:

External trigger mechanisms
Ringing (over shoots) - Poor design.
System noise
System power-up and power-down
(if inputs are generated from a different supply).
Forward biased junctions at input/output pins
V at input > Vcc
V at input < GND
Worst at elevated temperatures.

Internal Chip trigger mechanisms
Forward biased junctions on chip - design, layout, device.
Impact ionization - design
C dV/dT current - design, layout, external noise
Punchthrough current - device, process
Field inversion - process
Junction leakage (light) - process
Defects (fab and reliability failures)

Hope this is helpful.



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