Here is Larry's input to my inductance problem.
I appreciate the input. :)
*************************
Thank you |
Don Abernathey |
(503)690-6234 |
[email protected] |
*************************
--- Forwarded mail from [email protected] (Larry Smith)
Date: Mon, 25 Nov 1996 14:07:57 -0800
From: [email protected] (Larry Smith)
To: [email protected]
Subject: Re: Help with decoupling cap inductance
Don - I did some finite element (Ansoft) modeling of a structure similar
to yours, and decided the loop inductance was about .85 nH.
My structure was an 805 size capacitor sitting on solder pads with vias
to the power and ground planes at the outside edges of the pads:
+-------+ +-------+
| | | |
| +--------------+ |
- | | -
/ | | \
| O | | O |
\ | | /
- | | -
| +--------------+ |
| | | |
+-------+ +-------+
cap: 80x50 mils
pad: 40x?? mils
space: 60 mils (therefor, via pitch was 100 mils)
via pad: 30 mils
via barrel: 12 mils
via depth to 1st power plane: 14 mils
I assumed that the capacitor was a perfect conductor because I wanted the
loop inductance at high frequency. This will make my answer a bit low
because current really travels through the capacitor body, which is further
above the PCB power planes. The most important part of the problem is the
space between the vias (100 mils), via diameter and depth to the power
planes.
This determines the loop area that current must go around. I put a 2d
current
source in one of the vias to force current around the loop. Ansoft told
me there was some amount of energy when I forced 1 amp. Energy is 1/2 L*I*I,
so loop inductance was easily calculated to be .85 nH.
Your vias are a long way apart (215 mils). You have further to go to your
power planes (probably 20 mils if copper thickness is included). My guess
is that your loop inductance is closer to 2.61 nH. You might want to go
negotiate with manufacturing to put those vias in the pads.
regards,
Larry Smith
Sun Microelectronics
----- Begin Included Message -----
>From [email protected] Mon Nov 25 10:13:18 1996
From: "Don Abernathey" <[email protected]>
Date: Mon, 25 Nov 1996 10:12:49 -0800
To: [email protected]
Subject: Help with decoupling cap inductance
Cc: [email protected]
Mime-Version: 1.0
Hello!
I don't have access to a 3D field solver and I'm not sure that I trust
hand calculations.
I need some help determining the inductance contribution of a via, as
part of the loop formed by an 0805-size MLC capacitor connected
between power and ground as is commonly done for IC decoupling
applications.
Here is a common layout for an 0805 SMT decoupling cap:
|<-----------------Total------------------->|
| | | | | | | |
|Via|Trace|Solder pad|Space|Solder pad|Trace|Via|
| | | | | | | |
VCC GND
Via = 25mil OD pad, 13mil drill, 10mil finished hole
Trace = 20mil long, 25mil wide
Solder pad = 50mil square pad
Space (distance between pads) = 40mil
Total (center to center) = 215mil
The following is a portion of the layer stackup of a board. The cap
layout described above be created on the pad layer. The GND via would
be connected to both layers 2 and 5. The VCC via would be connected to
layer 6.
1 ----Pad Layer----
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 3mil
2 ------------------------------------------------------------ GND
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
3 --signal---
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
4 --signal--
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
5 ------------------------------------------------------------ GND
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ BC 2mil
6 ------------------------------------------------------------ VCC
Er = 4.3, GND = 1oz, signals = 1/2oz.
Any input is appreciated.
*************************
Thank you |
Don Abernathey |
(503)690-6234 |
[email protected] |
*************************
----- End Included Message -----
---End of forwarded mail from [email protected] (Larry Smith)