You can also do it using a swept .DC analysis in SPICE, rather than
the slowly varying .TRANsient analysis.
> A (very) good driver will look like:
>
>
> Iout
> | -------
> | /
> | /
> | /
> | /
> | /
> | /
> |/
> --------------- Vout
> ___/
>
> The flattening out is due to the diode clamping.
Looks like you've got the plot backwards. Flattening in the direction
you've shown would be due to saturation. Diode clamping tends to
limit the voltage by causing a rapid increase in current. Swap
the axis labels.
> To get such a nice looking Iout vs Vout curve with CMOS devices
> is not trivial, and involves active circuits.
Actually, you can get a nice looking, linear I-V curve like this
by starting with a very strong (low impedance) buffer, and then
then adding a (linear) series resistance.
Regards,
Andy