> > Layers Sig4 and Sig5 use the Thermal layer as partial reference.
> (I hope it is a very small portion.)
It is small only if the dielectric layer thicknesses between layers
7-8-9 are asymmetrical.
If the dielectric layers are the same, if 8 is in the middle between
7 and 9, then the portion is 50%. This is determined by physics, not
by what you connect the Thermal plane to.
> > Do you want to couple circuit ground to chassis, and vice-versa, by
> way of this path?
> (first question : don't care, ...
But that means there may be a path for noise, clocks, etc. from your
circuit to get to the skins of the box, and radiate! (OK, maybe you
don't care, if this box is in orbit by itself.)
> > Will you add discrete capacitors from the Thermal layer to Gnd layers
> > in areas of high via and pin density, to help the return currents pass
> > between planes?
> (yes, there will be areas of high via and pin density - but, no, I
> wasn't planning on adding discrete capacitors between the circuit ground
> plane and thermal ground plane. There will always be a low inductance
> path, i.e. gnd plane, next to a signal layer. that should be enough,
A signal runs a few inches on layer 2. Its HF return current is
immediately under it on layer 3.
The signal then takes a via to layer 25, and runs a few inches more.
Its HF return current is on layer 24.
Question: How does the HF return current on layer 3 get to the HF
return current on layer 24? Only if there is a low inductance path
from layer 3 to layer 24, in the immediate vicinity of the signal via.
If you provide lots of direct via connections between all the Gnd
layers, all over the board, then it's OK.
The signal then takes a via to layer 5. The HF return current is
almost entirely in layer 6 (Vcc).
Then it takes a via to layer 8. About half the HF return current is
in layer 9 (Thermal).
How do _these_ HF return currents find paths to one another and to the
return currents in the Gnd layers?
Yes, you do have the intrinsic capacitance between adjacent plane
layers (i.e., between layers 7 and 9). But if the return current
needs to spread out a lot to find enough capacitance to get from one
layer to another, that means more inductance.
Where the via or pin density is high, not only is there less local
intrinsic capacitance (because the planes look like Swiss cheese), but
you end up pushing more total switching current through that small