RE: [SI-LIST] : Conducted EMC Testing of PLL jitter

Colin Brench ([email protected])
Tue, 29 Sep 98 16:06:56 EDT


The application of enough rf power to cause your power to groundplane
voltage to be modulated up to 200mV p-p would certainly cause things
to jitter though I don't know how you would know cause from effect.
Over a 1GHz bandwidth the impedance presented by the module will vary
significantly as probably will the coupling transformer.

A less drastic method would be to isolate the power to specific
devices and apply the rf to them one at a time. This could be done
though a small current transformer, with a ferrite, or with a very
small resistor. In this way you would be able to apply a known level
of noise and be able to check that it is realistic. (If the device is
extremely well decoupled you might need an unrealistic ammount of
power to induce 200mV p-p)

Good luck,

orginal message follows:-

Perhaps some of the EMI/EMC savvy people on the list have
some comments and/or opinions on how best to couple an
interfering RF signal into the power planes of a digital board
to accomplish some EMC testing.

Basically I have a system (CPU's, memory, PLL's etc.) that
runs at a clock rate of several hundred MHz. I need to do
some tests to evaluate what effect noise on the power planes
over the range of ~DC to 1GHz has on the PLL jitter.

I would like to inject a signal (in the range of ~DC to 1 GHz)
into the power planes (up to maybe 200 mv p-p amplitude) to
see how the PLL handles the noise on it's power feed.

I have a broadband (10KHz to 1GHz) amplifier that can provide
an excitation level of up to 20 watts into 50 ohms.

We believe the system power distribution system (planes, bypass
caps etc.) looks like a broadband 50 milliohm (or less) impedance.

The question is: would impedance matching the 50 ohm amplifier
impedance to the sub-ohm plane impedance by means of a broadband
ferrite transmission line transformer be a prudent thing to do,
or is there another accepted way of doing this?

Any comments or suggestions on alternate ways of evaluating the
jitter performance of a system PLL in response to power supply
noise over a wide bandwidth would be of interest.

Ray Anderson

Sun Microsystems Inc.
[email protected]

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