Re: decoupling/ bypass capacitors at connectors

Larry Smith (ldsmith@lisboa)
Tue, 4 Mar 1997 13:46:23 -0800

This is a very important discussion on the role of decoupling
capacitors near connectors. It is surprising how few people
understand that return current ALWAYS travels on the adjacent
reference plane, regardless if it is vdd or gnd or which way
the signal happens to be switching (high or low).

To extend this discussion, don't we have the same situation with a via
that goes through a multi-layer board? This is especially true if the
board has many layers including a pair of power/vdd planes near the top of
the board and a pair near the bottom of the board. There may even be
a field of vias where a wide bus makes a transition from one side of a
board to another. This is beginning to look a lot like a connector.

Decoupling between the power pairs will be important, just as in the
connector example below. I like to stitch all of the ground planes
together with a via in every square inch of the board, then decouple
each power plane often, all over the board. I haven't done the hard
analysis for this, but my feeling is that this should be good for .5 nSec
rise times. Any comments?

Larry Smith
Sun Microsystems

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>From howiej@sigcon.com Tue Mar 4 11:10:39 1997
Date: Tue, 4 Mar 97 11:06:04 PST
X-Sender: howiej@accessone.com (Unverified)
Mime-Version: 1.0
To: Joey K Sterzinger <Joey_K_Sterzinger@ccm2.hf.intel.com>
From: Howard Johnson <howiej@sigcon.com>
Subject: Re: decoupling/ bypass capacitors at connectors
Cc: si-list@silab.eng.sun.com

[question of general interest forwarded to the signal-integrity-list
email group // please feel free to respond to Mr. Sterzinger directly
if you have additional material]

Thanks for your interest in High-Speed Digital Design!

In response to your question below, bypass capacitors near
a connector serve an important purpose.

When you send a signal from a chip, through a connector,
to a daughter card, consider the path of the returning
signal current (current always makes a loop, there is
always a returning signal current path).
>From the destination, current will return
along the power/ground system of the daughtercard, staying
on WHATEVER PLANE IS CLOSEST TO THE SIGNAL. If that
happens to be the power (+5v) plane, the returning
current flows there, right under the trace. Eventually,
the returning signal current reaches the connector.

Now imagine the connector has lots of ground pins (but few power pins).
The returning current (on the +5v plane) must now jump to the ground plane,
then flow to a nearby connector ground pin, and go through the
connector ground pin to the other board. If there is no
bypass capacitor nearby to help the return current make the
jump between planes, the returning current will have to substantially divert
away from the signal current in order to get from plane
to plane. Such a diversion would cause both crosstalk and EMI.

The bypass capacitors provide a path for returning signal
currents to jump between power and ground planes as needed
before moving through a connector. They play the same
role on the other side of the connector, helping the returning
signal current quickly hop to whatever plane is closet to the
source trace on the motherboard.

With 2-ns-risetime and faster logic, I lay out a row of regular bypass
capacitors on one side of the connector. If I am using a very close
spacing between ground pins on the connector (to control
crosstalk), then I try to locate the capacitors within a couple
of ground pin spacings of the connector.

BIG HINT: when using "impedance matched" connectors for
very high-speed applications, signals to and from the connector
are *best* routed on layers adjacent to whichever plane is most
naturally conveyed through the return-current signal pins of the connector.

I hope this answers your question,
Dr. Howard Johnson

At 03:41 PM 2/24/97 PST, you wrote:
> Howard,
>
> I recently took the High Speed Digital Design class from you at Intel,
> Corp in Oregon. I had a question that I thought about after the
> course that I wanted to ask you. My question relates to decoupling
> caps placed around connectors. What purpose do they serve since they
> are so far away from the power pin of the component? (This pin is up
> on the card) Do they help with power or signal quality or EMI? What
> is your recommendation for placing these capacitors? (ie how many,
> what values, placement recommendations) Thank you for your time in
> answering my question.
> Ciao!
>
> Joey Sterzinger
> Intel Corporation
> (503)696-4672
>
>
_________________________________________________
Dr. Howard Johnson, Signal Consulting, Inc.
16541 Redmond Way, Suite 264, Redmond, WA 98052
U.S. tel (206) 556 0800 // fax 206 881 6149 // email howiej@sigcon.com
http://www.sigcon.com

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