I don't have access to a 3D field solver and I'm not sure that I trust
hand calculations.
I need some help determining the inductance contribution of a via, as
part of the loop formed by an 0805-size MLC capacitor connected
between power and ground as is commonly done for IC decoupling
applications.
Here is a common layout for an 0805 SMT decoupling cap:
|<-----------------Total------------------->|
| | | | | | | |
|Via|Trace|Solder pad|Space|Solder pad|Trace|Via|
| | | | | | | |
VCC GND
Via = 25mil OD pad, 13mil drill, 10mil finished hole
Trace = 20mil long, 25mil wide
Solder pad = 50mil square pad
Space (distance between pads) = 40mil
Total (center to center) = 215mil
The following is a portion of the layer stackup of a board. The cap
layout described above be created on the pad layer. The GND via would
be connected to both layers 2 and 5. The VCC via would be connected to
layer 6.
1 ----Pad Layer----
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 3mil
2 ------------------------------------------------------------ GND
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
3 --signal---
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
4 --signal--
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 5mil
5 ------------------------------------------------------------ GND
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ BC 2mil
6 ------------------------------------------------------------ VCC
Er = 4.3, GND = 1oz, signals = 1/2oz.
Any input is appreciated.
*************************
Thank you |
Don Abernathey |
(503)690-6234 |
[email protected] |
*************************