This is an excellent response by Jay Shenoy of VLSI.
As per his request, I'm forwarding this to the list
because it's been about 3 hours without receiving
a copy from the list exploder.
Received: from mail.hq.tellabs.com by tellab5.tellabs.com with smtp
(Smail126.96.36.199 #4) id m0zYv4R-003BN3C; Thu, 29 Oct 98 10:37 CST
Received: from mx.tellabs.com (mx.tellabs.com [188.8.131.52])
by mail.hq.tellabs.com (8.8.6/8.8.6) with ESMTP id KAA00838
for <firstname.lastname@example.org>; Thu, 29 Oct 1998 10:36:24 -0600 (CST)
Received: from relayhost.vlsi.com (relayhost.vlsi.com [184.108.40.206])
by mx.tellabs.com (8.8.8/8.8.8) with ESMTP id KAA21166
for <email@example.com>; Thu, 29 Oct 1998 10:36:12 -0600 (CST)
Received: (from smtp@localhost) by relayhost.vlsi.com (SMI-8.6/) id IAA10475; Thu, 29 Oct 1998 08:36:00 -0800
Received: from <Jay.Shenoy@VLSI.com> (sjc-aluminum.sanjose.vlsi.com [220.127.116.11]) by isis.vlsi.com via smap (V2.0)
id xma010471; Thu, 29 Oct 98 08:35:55 -0800
Received: by sjc-aluminum with Internet Mail Service (5.5.2232.9)
id <4TCB1HKC>; Thu, 29 Oct 1998 08:34:36 -0800
From: "Shenoy, Jay" <Jay.Shenoy@VLSI.com>
To: "'Dennis Tomlinson'" <firstname.lastname@example.org>,
Cc: "Shenoy, Jay" <Jay.Shenoy@VLSI.com>
Subject: RE: [SI-LIST] : Schottky diode termination
Date: Thu, 29 Oct 1998 08:35:47 -0800
X-Mailer: Internet Mail Service (5.5.2232.9)
X-MIME-Autoconverted: from 8bit to quoted-printable by mail.hq.tellabs.com id KAA00838
To provide my 2 cents worth to Dennis' queries:
>1. Do the semiconductor companies ascribe and/or acquiesce to the
use of CMOS
input clamp diodes for line termination?
I'm not sure semiconductor companies think about termination when
ESD structures, and having been involved in both ESD and signal
integrity, & IMHO the=20
requirements for the former are "looser" than the latter.=20
Specifically, ESD clamps need to clamp the voltage so that the
structures are not damaged. In terms of voltage (not an accurate way
of specifying for ESD)
this could be 1.5 X (or more) of the supply voltage for that
allows for a lot of ringing, *especially* with reduced swing I/O's
like HSTL when run=20
underterminated or unterminated.
>2. What are typical limits for "one time" peak currents?
This can be easily guessed at from the HBM (human body model)
spec of the manufacturer.
HBM has a 1500 ohm resistance in the spec, and so peak current =3D
peak HBM voltage/ 1500.
Typical HBM specs are 1500 V, so 1000 mA "one time" (and this would
really be one time)=20
peak currents could be sunk by good clamping structures. (Maybe the
folks will appreciate why capacitances of ESD structures sometimes
appear so large :-) ).
Sanity check on above, grounded gate protection MOSFET structures,
most generic in
sub-micron processes sink 5-10 mA/micron width in *clamp* mode, and
typically a few 100's
of microns of width are generally provided in I/O's. CDM (Charged
device model) is more=20
tricky to simplify in this fashion, but manufacturer *has* to meet
HBM spec too, and so it=20
can't be any lower than the above estimation.
(Am I missing something, I was a little surprised by 1000 mA
myself, but cant find any arithmetic
On 3), I'd have to think a little bit harder (by repetitive, I
assume you mean impulse currents
every cycle), and I'm not sure unambiguous answers would be easy to
come by. Because=20
clamping structures are _not_ designed for this kind of use
generally. They won't even kick in
until 1.3-1.5X (probably more ) of supply voltage, which is what I
think is the main problem with
them. But your example being 10X lower than what would be a typical
peak current seems to=20
give enough margin.
Oh, by the way, many things I said here applies to CMOS/NMOS
technologies only. The list
obviously has a broader technological base, but we in the CMOS world
often forget that there
are other things :-).
ps to Dennis, if this doesn't make it to the list (a couple of my
previous mails have never appeared
on my site) could you forward it? Thanks.
> -----Original Message-----
> From: Dennis Tomlinson [SMTP:email@example.com]
> Sent: Wednesday, October 28, 1998 9:07 AM
> To: 'si-list'
> Subject: Re: [SI-LIST] : Schottky diode termination
> Andrew Ingraham wrote:
> > John,
> > I first saw Schottky diode termination described in a rather old
> > Fairchild ECL book. Diode termination was not often used for ECL,
> > perhaps because the normal ECL parallel termination usually worked qu=
> > well if you could afford the power dissipation.
> > The TTL logic families had clamp diodes in their input structures, an=
> > one of their intended functions actually was to provide some amount o=
> > diode termination. This is one of the reasons why TTL was easy to wo=
> > with, sometimes even when the wires got long compared to the falltime=
> > Many people who have used TTL do not realize that they have been maki=
> > use of diode termination all along.
> > Most CMOS families also have input clamp diodes, and again they
> > generally work as both input protection and partial signal terminatio=
> Andrew, John, list,
> It has long been my belief that the input clamp diodes on CMOS are for
> the purpose of providing ESD protection, and for clamping the "occasion=
> over/undershoot. They are not provided for the purpose of providing lin=
> termination. My belief is based on verbal communiqu=E9 with cohorts and
> apps. engineers (which is to say, it could be based on legend and=20
> As a crude example, suppose a full 5V transition is launched onto an
> electrically long 50 Ohm line, causing the propagation of a 100 mA=20
> current wave. With no other termination or loads, and assuming a clamp=20
> forward bias of about 1V, this would require the clamp diode to conduct=
> a peak current of about 80 mA. If this were a highly repetitive signal,=
> the duty cycle for each diode could approach 50%. I would expect seriou=
> MTBF issues with this scenario. I would also expect the semiconductor
> types on this list to shudder at the thought of such an abusive
> (aside from the strong possibility that the circuit may not function
> I would like to pose some related questions for anyone on the list - mo=
> particularly the semiconductor types:
> 1. Do the semiconductor companies ascribe and/or acquiesce to the use o=
> input clamp diodes for line termination?
> 2. What are typical limits for "one time" peak currents?
> 3. What are typical limits for repetitive peak currents?
> 4. What if I were to change the example above such that the driver
> launched a=20
> 3.5 volt wave (70 mA)? The clamp current would then peak at roughly =
> 5. And finally, what if the line length were shorter, so that the clamp
> duty cycle were only a few percent?
> > Those CMOS devices without input diodes tend to be SI nightmares.
> > In a multi-drop bus configuration, diode terminators may be needed at
> > several places, perhaps as many as one per input. For a daisy-chain
> > route, they may only be needed at the two ends. The best way to tell
> > what works is to try, preferably in simulation with GOOD models.
> > Regards,
> > Andy Ingraham
> **** To unsubscribe from si-list: send e-mail to
> firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
> si-list, for more help, put HELP. si-list archives are accessible at
> http://www.qsl.net/wb6tpu/si-list ****
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****