Re: [SI-LIST] : Decoupling capacitors

efy@ccrl.nj.nec.com
Tue, 11 Aug 1998 18:44:04 -0400

> > What do you think about the "common" practice to place bypass capacitors
> > on the solder side of the board right under the IC located on the
> > component side and use vias to connect to VCC and gnd the capacitor. I
> > certainly don't recommend to do that but I have seen it so many times I
> > wonder if in some cases it is justified.
> > Any comments
> >
> > --
> > Philippe Poulet
>
> The objective is to get the least amount of impedance (inductance)
> between the power consumer (asic) and charge storage (capacitor).
> That is usually accomplished by placing vias from the cap to the power
> planes, and then vias from the power planes to the asic. Traces
> make a lot of inductance. Manufacturing soldering rules generally

Does it mean then that the capacitors can be placed freely around the chip
to ease placement and routing and they don't have to be placed as close as
possible to pwr or gnd pins?

> do not allow you to put a via directly under a surface mount pad
> for an asic or a capacitor (at least with IR reflow).
>
> regards,
> Larry Smith
> Sun Microsystems

Thank you,
Eldar Yuzbashev
NEC USA, Inc.