Re: [SI-LIST] : data bus clash - how bad?

Larry Smith ([email protected])
Sun, 11 Jan 1998 20:48:14 -0800 (PST)

Andrew - If the clash on the data bus is shorter than the time of
flight, then it will probably not be too bad.

I assume that the clash is between two chips located some distance
away from each other. By "clash" I assume you mean that one chip may
be trying to drive the bus high at the same instant in time that
another chip is trying to drive it low. If the chips were physically
on top of each other, a lot of current would flow from power to ground.

But, if there is a time of flight (1 nSec or so) from one chip to the
another, the problem will not be as bad. The driver that is becoming
high impedance will have turned off by the time the new signal
reaches it. It will simply appear to be a capacitive load when the
signal gets there. The bus will be terminated as it always was,
probably by the output impedance of the new driver.

But, if the clash lasts longer than the time of flight between
the two offending drivers, current will double at the far end
(rather than voltage doubling) and a nasty reflection will occur.
That will be trouble.

Larry Smith
Sun Microsystems

> Date: Mon, 12 Jan 1998 10:22:32 +0800
> From: Andrew Phillips <[email protected]>
> Mime-Version: 1.0
> To: SI-LIST <[email protected]>
> Subject: [SI-LIST] : data bus clash - how bad?
> Content-Transfer-Encoding: 7bit
> Hi all,
> I have been doing a timing analysis for an interface between a processor
> and SRAM. During a read/write cycle turnaround I have hit on the
> situation where in absolute worst-case conditions there can be a clash
> on the data bus.
> I have always tried to avoid such a situation having been told that this
> causes large transient currents leading to excessive board noise and
> reduces the reliability of the I/O drivers and other such fire and
> brimstone ...
> I am wondering whether anyone has done some closer analysis on this
> subject. I presume that the severity of the problem will depend on a
> number of things such as:
> - how long the clash can potentially last for
> - how much loss due to back-matching resistors is provided
> - how long the traces are
> Any hints on how to determine how bad such a situation would really be?
> Thanks,
> Andrew Phillips
> Supercomputing Systems AG
> Zurich, Switzerland